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// Copyright (c) 1994-2006 Sun Microsystems Inc.
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// All Rights Reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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//
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// - Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimer.
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//
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// - Redistribution in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the
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// distribution.
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//
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// - Neither the name of Sun Microsystems or the names of contributors may
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// be used to endorse or promote products derived from this software without
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// specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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// HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
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// OF THE POSSIBILITY OF SUCH DAMAGE.
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// The original source code covered by the above license above has been modified
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// significantly by Google Inc.
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// Copyright 2006-2008 the V8 project authors. All rights reserved.
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#ifndef V8_ARM_ASSEMBLER_ARM_INL_H_
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#define V8_ARM_ASSEMBLER_ARM_INL_H_
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#include "arm/assembler-arm.h"
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#include "cpu.h"
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namespace v8 {
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namespace internal {
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Condition NegateCondition(Condition cc) {
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ASSERT(cc != al);
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return static_cast<Condition>(cc ^ ne);
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}
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void RelocInfo::apply(intptr_t delta) {
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if (RelocInfo::IsInternalReference(rmode_)) {
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// absolute code pointer inside code object moves with the code object.
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int32_t* p = reinterpret_cast<int32_t*>(pc_);
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*p += delta; // relocate entry
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}
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// We do not use pc relative addressing on ARM, so there is
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// nothing else to do.
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}
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Address RelocInfo::target_address() {
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ASSERT(IsCodeTarget(rmode_) || rmode_ == RUNTIME_ENTRY);
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return Assembler::target_address_at(pc_);
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}
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Address RelocInfo::target_address_address() {
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ASSERT(IsCodeTarget(rmode_) || rmode_ == RUNTIME_ENTRY);
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return reinterpret_cast<Address>(Assembler::target_address_address_at(pc_));
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}
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void RelocInfo::set_target_address(Address target) {
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ASSERT(IsCodeTarget(rmode_) || rmode_ == RUNTIME_ENTRY);
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Assembler::set_target_address_at(pc_, target);
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}
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Object* RelocInfo::target_object() {
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ASSERT(IsCodeTarget(rmode_) || rmode_ == EMBEDDED_OBJECT);
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return Memory::Object_at(Assembler::target_address_address_at(pc_));
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}
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Handle<Object> RelocInfo::target_object_handle(Assembler* origin) {
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ASSERT(IsCodeTarget(rmode_) || rmode_ == EMBEDDED_OBJECT);
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return Memory::Object_Handle_at(Assembler::target_address_address_at(pc_));
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}
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Object** RelocInfo::target_object_address() {
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ASSERT(IsCodeTarget(rmode_) || rmode_ == EMBEDDED_OBJECT);
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return reinterpret_cast<Object**>(Assembler::target_address_address_at(pc_));
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}
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void RelocInfo::set_target_object(Object* target) {
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ASSERT(IsCodeTarget(rmode_) || rmode_ == EMBEDDED_OBJECT);
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Assembler::set_target_address_at(pc_, reinterpret_cast<Address>(target));
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}
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Address* RelocInfo::target_reference_address() {
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ASSERT(rmode_ == EXTERNAL_REFERENCE);
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return reinterpret_cast<Address*>(Assembler::target_address_address_at(pc_));
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}
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Address RelocInfo::call_address() {
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ASSERT(IsPatchedReturnSequence());
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// The 2 instructions offset assumes patched return sequence.
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ASSERT(IsJSReturn(rmode()));
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return Memory::Address_at(pc_ + 2 * Assembler::kInstrSize);
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}
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void RelocInfo::set_call_address(Address target) {
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ASSERT(IsPatchedReturnSequence());
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// The 2 instructions offset assumes patched return sequence.
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ASSERT(IsJSReturn(rmode()));
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Memory::Address_at(pc_ + 2 * Assembler::kInstrSize) = target;
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}
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Object* RelocInfo::call_object() {
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return *call_object_address();
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}
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Object** RelocInfo::call_object_address() {
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ASSERT(IsPatchedReturnSequence());
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// The 2 instructions offset assumes patched return sequence.
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ASSERT(IsJSReturn(rmode()));
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return reinterpret_cast<Object**>(pc_ + 2 * Assembler::kInstrSize);
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}
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void RelocInfo::set_call_object(Object* target) {
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*call_object_address() = target;
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}
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bool RelocInfo::IsPatchedReturnSequence() {
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// On ARM a "call instruction" is actually two instructions.
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// mov lr, pc
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// ldr pc, [pc, #XXX]
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return (Assembler::instr_at(pc_) == kMovLrPc)
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&& ((Assembler::instr_at(pc_ + Assembler::kInstrSize) & kLdrPCPattern)
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== kLdrPCPattern);
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}
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Operand::Operand(int32_t immediate, RelocInfo::Mode rmode) {
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rm_ = no_reg;
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imm32_ = immediate;
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rmode_ = rmode;
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}
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Operand::Operand(const char* s) {
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rm_ = no_reg;
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imm32_ = reinterpret_cast<int32_t>(s);
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rmode_ = RelocInfo::EMBEDDED_STRING;
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}
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Operand::Operand(const ExternalReference& f) {
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rm_ = no_reg;
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imm32_ = reinterpret_cast<int32_t>(f.address());
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rmode_ = RelocInfo::EXTERNAL_REFERENCE;
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}
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Operand::Operand(Object** opp) {
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rm_ = no_reg;
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imm32_ = reinterpret_cast<int32_t>(opp);
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rmode_ = RelocInfo::NONE;
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}
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Operand::Operand(Context** cpp) {
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rm_ = no_reg;
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imm32_ = reinterpret_cast<int32_t>(cpp);
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rmode_ = RelocInfo::NONE;
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}
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Operand::Operand(Smi* value) {
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rm_ = no_reg;
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imm32_ = reinterpret_cast<intptr_t>(value);
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rmode_ = RelocInfo::NONE;
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}
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Operand::Operand(Register rm) {
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rm_ = rm;
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rs_ = no_reg;
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shift_op_ = LSL;
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shift_imm_ = 0;
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}
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bool Operand::is_reg() const {
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return rm_.is_valid() &&
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rs_.is(no_reg) &&
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shift_op_ == LSL &&
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shift_imm_ == 0;
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}
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void Assembler::CheckBuffer() {
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if (buffer_space() <= kGap) {
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GrowBuffer();
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}
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if (pc_offset() >= next_buffer_check_) {
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CheckConstPool(false, true);
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}
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}
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void Assembler::emit(Instr x) {
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CheckBuffer();
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*reinterpret_cast<Instr*>(pc_) = x;
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pc_ += kInstrSize;
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}
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Address Assembler::target_address_address_at(Address pc) {
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Instr instr = Memory::int32_at(pc);
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// Verify that the instruction at pc is a ldr<cond> <Rd>, [pc +/- offset_12].
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ASSERT((instr & 0x0f7f0000) == 0x051f0000);
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int offset = instr & 0xfff; // offset_12 is unsigned
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if ((instr & (1 << 23)) == 0) offset = -offset; // U bit defines offset sign
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// Verify that the constant pool comes after the instruction referencing it.
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ASSERT(offset >= -4);
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return pc + offset + 8;
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}
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Address Assembler::target_address_at(Address pc) {
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return Memory::Address_at(target_address_address_at(pc));
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}
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void Assembler::set_target_at(Address constant_pool_entry,
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Address target) {
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Memory::Address_at(constant_pool_entry) = target;
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}
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void Assembler::set_target_address_at(Address pc, Address target) {
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Memory::Address_at(target_address_address_at(pc)) = target;
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// Intuitively, we would think it is necessary to flush the instruction cache
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// after patching a target address in the code as follows:
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// CPU::FlushICache(pc, sizeof(target));
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// However, on ARM, no instruction was actually patched by the assignment
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// above; the target address is not part of an instruction, it is patched in
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// the constant pool and is read via a data access; the instruction accessing
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// this address in the constant pool remains unchanged.
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}
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} } // namespace v8::internal
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#endif // V8_ARM_ASSEMBLER_ARM_INL_H_
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