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2663 lines
82 KiB
2663 lines
82 KiB
// Copyright (c) 1994-2006 Sun Microsystems Inc.
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// All Rights Reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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//
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// - Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimer.
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//
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// - Redistribution in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the
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// distribution.
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//
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// - Neither the name of Sun Microsystems or the names of contributors may
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// be used to endorse or promote products derived from this software without
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// specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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// HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
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// OF THE POSSIBILITY OF SUCH DAMAGE.
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// The original source code covered by the above license above has been
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// modified significantly by Google Inc.
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// Copyright 2011 the V8 project authors. All rights reserved.
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#include "v8.h"
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#if defined(V8_TARGET_ARCH_ARM)
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#include "arm/assembler-arm-inl.h"
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#include "serialize.h"
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namespace v8 {
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namespace internal {
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#ifdef DEBUG
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bool CpuFeatures::initialized_ = false;
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#endif
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unsigned CpuFeatures::supported_ = 0;
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unsigned CpuFeatures::found_by_runtime_probing_ = 0;
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// Get the CPU features enabled by the build. For cross compilation the
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// preprocessor symbols CAN_USE_ARMV7_INSTRUCTIONS and CAN_USE_VFP_INSTRUCTIONS
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// can be defined to enable ARMv7 and VFPv3 instructions when building the
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// snapshot.
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static uint64_t CpuFeaturesImpliedByCompiler() {
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uint64_t answer = 0;
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#ifdef CAN_USE_ARMV7_INSTRUCTIONS
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answer |= 1u << ARMv7;
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#endif // def CAN_USE_ARMV7_INSTRUCTIONS
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#ifdef CAN_USE_VFP_INSTRUCTIONS
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answer |= 1u << VFP3 | 1u << ARMv7;
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#endif // def CAN_USE_VFP_INSTRUCTIONS
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#ifdef __arm__
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// If the compiler is allowed to use VFP then we can use VFP too in our code
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// generation even when generating snapshots. This won't work for cross
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// compilation. VFPv3 implies ARMv7, see ARM DDI 0406B, page A1-6.
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#if defined(__VFP_FP__) && !defined(__SOFTFP__)
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answer |= 1u << VFP3 | 1u << ARMv7;
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#endif // defined(__VFP_FP__) && !defined(__SOFTFP__)
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#endif // def __arm__
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return answer;
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}
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void CpuFeatures::Probe() {
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unsigned standard_features = (OS::CpuFeaturesImpliedByPlatform() |
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CpuFeaturesImpliedByCompiler());
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ASSERT(supported_ == 0 || supported_ == standard_features);
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#ifdef DEBUG
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initialized_ = true;
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#endif
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// Get the features implied by the OS and the compiler settings. This is the
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// minimal set of features which is also alowed for generated code in the
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// snapshot.
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supported_ |= standard_features;
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if (Serializer::enabled()) {
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// No probing for features if we might serialize (generate snapshot).
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return;
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}
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#ifndef __arm__
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// For the simulator=arm build, use VFP when FLAG_enable_vfp3 is
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// enabled. VFPv3 implies ARMv7, see ARM DDI 0406B, page A1-6.
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if (FLAG_enable_vfp3) {
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supported_ |= 1u << VFP3 | 1u << ARMv7;
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}
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// For the simulator=arm build, use ARMv7 when FLAG_enable_armv7 is enabled
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if (FLAG_enable_armv7) {
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supported_ |= 1u << ARMv7;
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}
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#else // def __arm__
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// Probe for additional features not already known to be available.
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if (!IsSupported(VFP3) && OS::ArmCpuHasFeature(VFP3)) {
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// This implementation also sets the VFP flags if runtime
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// detection of VFP returns true. VFPv3 implies ARMv7, see ARM DDI
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// 0406B, page A1-6.
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supported_ |= 1u << VFP3 | 1u << ARMv7;
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found_by_runtime_probing_ |= 1u << VFP3 | 1u << ARMv7;
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}
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if (!IsSupported(ARMv7) && OS::ArmCpuHasFeature(ARMv7)) {
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supported_ |= 1u << ARMv7;
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found_by_runtime_probing_ |= 1u << ARMv7;
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}
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#endif
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}
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// -----------------------------------------------------------------------------
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// Implementation of RelocInfo
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const int RelocInfo::kApplyMask = 0;
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bool RelocInfo::IsCodedSpecially() {
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// The deserializer needs to know whether a pointer is specially coded. Being
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// specially coded on ARM means that it is a movw/movt instruction. We don't
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// generate those yet.
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return false;
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}
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void RelocInfo::PatchCode(byte* instructions, int instruction_count) {
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// Patch the code at the current address with the supplied instructions.
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Instr* pc = reinterpret_cast<Instr*>(pc_);
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Instr* instr = reinterpret_cast<Instr*>(instructions);
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for (int i = 0; i < instruction_count; i++) {
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*(pc + i) = *(instr + i);
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}
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// Indicate that code has changed.
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CPU::FlushICache(pc_, instruction_count * Assembler::kInstrSize);
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}
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// Patch the code at the current PC with a call to the target address.
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// Additional guard instructions can be added if required.
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void RelocInfo::PatchCodeWithCall(Address target, int guard_bytes) {
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// Patch the code at the current address with a call to the target.
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UNIMPLEMENTED();
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}
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// -----------------------------------------------------------------------------
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// Implementation of Operand and MemOperand
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// See assembler-arm-inl.h for inlined constructors
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Operand::Operand(Handle<Object> handle) {
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rm_ = no_reg;
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// Verify all Objects referred by code are NOT in new space.
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Object* obj = *handle;
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ASSERT(!HEAP->InNewSpace(obj));
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if (obj->IsHeapObject()) {
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imm32_ = reinterpret_cast<intptr_t>(handle.location());
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rmode_ = RelocInfo::EMBEDDED_OBJECT;
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} else {
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// no relocation needed
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imm32_ = reinterpret_cast<intptr_t>(obj);
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rmode_ = RelocInfo::NONE;
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}
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}
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Operand::Operand(Register rm, ShiftOp shift_op, int shift_imm) {
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ASSERT(is_uint5(shift_imm));
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ASSERT(shift_op != ROR || shift_imm != 0); // use RRX if you mean it
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rm_ = rm;
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rs_ = no_reg;
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shift_op_ = shift_op;
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shift_imm_ = shift_imm & 31;
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if (shift_op == RRX) {
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// encoded as ROR with shift_imm == 0
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ASSERT(shift_imm == 0);
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shift_op_ = ROR;
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shift_imm_ = 0;
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}
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}
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Operand::Operand(Register rm, ShiftOp shift_op, Register rs) {
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ASSERT(shift_op != RRX);
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rm_ = rm;
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rs_ = no_reg;
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shift_op_ = shift_op;
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rs_ = rs;
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}
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MemOperand::MemOperand(Register rn, int32_t offset, AddrMode am) {
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rn_ = rn;
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rm_ = no_reg;
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offset_ = offset;
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am_ = am;
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}
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MemOperand::MemOperand(Register rn, Register rm, AddrMode am) {
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rn_ = rn;
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rm_ = rm;
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shift_op_ = LSL;
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shift_imm_ = 0;
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am_ = am;
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}
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MemOperand::MemOperand(Register rn, Register rm,
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ShiftOp shift_op, int shift_imm, AddrMode am) {
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ASSERT(is_uint5(shift_imm));
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rn_ = rn;
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rm_ = rm;
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shift_op_ = shift_op;
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shift_imm_ = shift_imm & 31;
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am_ = am;
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}
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// -----------------------------------------------------------------------------
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// Specific instructions, constants, and masks.
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// add(sp, sp, 4) instruction (aka Pop())
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const Instr kPopInstruction =
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al | PostIndex | 4 | LeaveCC | I | sp.code() * B16 | sp.code() * B12;
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// str(r, MemOperand(sp, 4, NegPreIndex), al) instruction (aka push(r))
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// register r is not encoded.
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const Instr kPushRegPattern =
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al | B26 | 4 | NegPreIndex | sp.code() * B16;
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// ldr(r, MemOperand(sp, 4, PostIndex), al) instruction (aka pop(r))
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// register r is not encoded.
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const Instr kPopRegPattern =
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al | B26 | L | 4 | PostIndex | sp.code() * B16;
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// mov lr, pc
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const Instr kMovLrPc = al | MOV | pc.code() | lr.code() * B12;
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// ldr rd, [pc, #offset]
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const Instr kLdrPCMask = kCondMask | 15 * B24 | 7 * B20 | 15 * B16;
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const Instr kLdrPCPattern = al | 5 * B24 | L | pc.code() * B16;
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// blxcc rm
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const Instr kBlxRegMask =
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15 * B24 | 15 * B20 | 15 * B16 | 15 * B12 | 15 * B8 | 15 * B4;
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const Instr kBlxRegPattern =
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B24 | B21 | 15 * B16 | 15 * B12 | 15 * B8 | BLX;
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const Instr kMovMvnMask = 0x6d * B21 | 0xf * B16;
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const Instr kMovMvnPattern = 0xd * B21;
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const Instr kMovMvnFlip = B22;
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const Instr kMovLeaveCCMask = 0xdff * B16;
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const Instr kMovLeaveCCPattern = 0x1a0 * B16;
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const Instr kMovwMask = 0xff * B20;
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const Instr kMovwPattern = 0x30 * B20;
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const Instr kMovwLeaveCCFlip = 0x5 * B21;
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const Instr kCmpCmnMask = 0xdd * B20 | 0xf * B12;
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const Instr kCmpCmnPattern = 0x15 * B20;
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const Instr kCmpCmnFlip = B21;
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const Instr kAddSubFlip = 0x6 * B21;
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const Instr kAndBicFlip = 0xe * B21;
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// A mask for the Rd register for push, pop, ldr, str instructions.
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const Instr kLdrRegFpOffsetPattern =
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al | B26 | L | Offset | fp.code() * B16;
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const Instr kStrRegFpOffsetPattern =
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al | B26 | Offset | fp.code() * B16;
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const Instr kLdrRegFpNegOffsetPattern =
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al | B26 | L | NegOffset | fp.code() * B16;
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const Instr kStrRegFpNegOffsetPattern =
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al | B26 | NegOffset | fp.code() * B16;
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const Instr kLdrStrInstrTypeMask = 0xffff0000;
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const Instr kLdrStrInstrArgumentMask = 0x0000ffff;
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const Instr kLdrStrOffsetMask = 0x00000fff;
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// Spare buffer.
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static const int kMinimalBufferSize = 4*KB;
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Assembler::Assembler(Isolate* arg_isolate, void* buffer, int buffer_size)
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: AssemblerBase(arg_isolate),
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positions_recorder_(this),
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emit_debug_code_(FLAG_debug_code) {
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if (buffer == NULL) {
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// Do our own buffer management.
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if (buffer_size <= kMinimalBufferSize) {
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buffer_size = kMinimalBufferSize;
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if (isolate()->assembler_spare_buffer() != NULL) {
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buffer = isolate()->assembler_spare_buffer();
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isolate()->set_assembler_spare_buffer(NULL);
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}
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}
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if (buffer == NULL) {
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buffer_ = NewArray<byte>(buffer_size);
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} else {
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buffer_ = static_cast<byte*>(buffer);
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}
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buffer_size_ = buffer_size;
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own_buffer_ = true;
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} else {
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// Use externally provided buffer instead.
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ASSERT(buffer_size > 0);
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buffer_ = static_cast<byte*>(buffer);
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buffer_size_ = buffer_size;
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own_buffer_ = false;
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}
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// Set up buffer pointers.
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ASSERT(buffer_ != NULL);
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pc_ = buffer_;
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reloc_info_writer.Reposition(buffer_ + buffer_size, pc_);
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num_pending_reloc_info_ = 0;
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next_buffer_check_ = 0;
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const_pool_blocked_nesting_ = 0;
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no_const_pool_before_ = 0;
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first_const_pool_use_ = -1;
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last_bound_pos_ = 0;
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ClearRecordedAstId();
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}
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Assembler::~Assembler() {
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ASSERT(const_pool_blocked_nesting_ == 0);
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if (own_buffer_) {
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if (isolate()->assembler_spare_buffer() == NULL &&
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buffer_size_ == kMinimalBufferSize) {
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isolate()->set_assembler_spare_buffer(buffer_);
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} else {
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DeleteArray(buffer_);
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}
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}
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}
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void Assembler::GetCode(CodeDesc* desc) {
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// Emit constant pool if necessary.
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CheckConstPool(true, false);
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ASSERT(num_pending_reloc_info_ == 0);
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// Set up code descriptor.
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desc->buffer = buffer_;
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desc->buffer_size = buffer_size_;
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desc->instr_size = pc_offset();
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desc->reloc_size = (buffer_ + buffer_size_) - reloc_info_writer.pos();
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}
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void Assembler::Align(int m) {
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ASSERT(m >= 4 && IsPowerOf2(m));
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while ((pc_offset() & (m - 1)) != 0) {
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nop();
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}
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}
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void Assembler::CodeTargetAlign() {
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// Preferred alignment of jump targets on some ARM chips.
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Align(8);
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}
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Condition Assembler::GetCondition(Instr instr) {
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return Instruction::ConditionField(instr);
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}
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bool Assembler::IsBranch(Instr instr) {
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return (instr & (B27 | B25)) == (B27 | B25);
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}
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int Assembler::GetBranchOffset(Instr instr) {
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ASSERT(IsBranch(instr));
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// Take the jump offset in the lower 24 bits, sign extend it and multiply it
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// with 4 to get the offset in bytes.
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return ((instr & kImm24Mask) << 8) >> 6;
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}
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bool Assembler::IsLdrRegisterImmediate(Instr instr) {
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return (instr & (B27 | B26 | B25 | B22 | B20)) == (B26 | B20);
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}
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int Assembler::GetLdrRegisterImmediateOffset(Instr instr) {
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ASSERT(IsLdrRegisterImmediate(instr));
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bool positive = (instr & B23) == B23;
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int offset = instr & kOff12Mask; // Zero extended offset.
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return positive ? offset : -offset;
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}
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Instr Assembler::SetLdrRegisterImmediateOffset(Instr instr, int offset) {
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ASSERT(IsLdrRegisterImmediate(instr));
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bool positive = offset >= 0;
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if (!positive) offset = -offset;
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ASSERT(is_uint12(offset));
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// Set bit indicating whether the offset should be added.
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instr = (instr & ~B23) | (positive ? B23 : 0);
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// Set the actual offset.
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return (instr & ~kOff12Mask) | offset;
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}
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bool Assembler::IsStrRegisterImmediate(Instr instr) {
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return (instr & (B27 | B26 | B25 | B22 | B20)) == B26;
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}
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Instr Assembler::SetStrRegisterImmediateOffset(Instr instr, int offset) {
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ASSERT(IsStrRegisterImmediate(instr));
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bool positive = offset >= 0;
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if (!positive) offset = -offset;
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ASSERT(is_uint12(offset));
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// Set bit indicating whether the offset should be added.
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instr = (instr & ~B23) | (positive ? B23 : 0);
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// Set the actual offset.
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return (instr & ~kOff12Mask) | offset;
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}
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bool Assembler::IsAddRegisterImmediate(Instr instr) {
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return (instr & (B27 | B26 | B25 | B24 | B23 | B22 | B21)) == (B25 | B23);
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}
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Instr Assembler::SetAddRegisterImmediateOffset(Instr instr, int offset) {
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ASSERT(IsAddRegisterImmediate(instr));
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ASSERT(offset >= 0);
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ASSERT(is_uint12(offset));
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// Set the offset.
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return (instr & ~kOff12Mask) | offset;
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}
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Register Assembler::GetRd(Instr instr) {
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Register reg;
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reg.code_ = Instruction::RdValue(instr);
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return reg;
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}
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Register Assembler::GetRn(Instr instr) {
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Register reg;
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reg.code_ = Instruction::RnValue(instr);
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return reg;
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}
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Register Assembler::GetRm(Instr instr) {
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Register reg;
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reg.code_ = Instruction::RmValue(instr);
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return reg;
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}
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bool Assembler::IsPush(Instr instr) {
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return ((instr & ~kRdMask) == kPushRegPattern);
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}
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bool Assembler::IsPop(Instr instr) {
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return ((instr & ~kRdMask) == kPopRegPattern);
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}
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bool Assembler::IsStrRegFpOffset(Instr instr) {
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return ((instr & kLdrStrInstrTypeMask) == kStrRegFpOffsetPattern);
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}
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bool Assembler::IsLdrRegFpOffset(Instr instr) {
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return ((instr & kLdrStrInstrTypeMask) == kLdrRegFpOffsetPattern);
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}
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bool Assembler::IsStrRegFpNegOffset(Instr instr) {
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return ((instr & kLdrStrInstrTypeMask) == kStrRegFpNegOffsetPattern);
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}
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bool Assembler::IsLdrRegFpNegOffset(Instr instr) {
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return ((instr & kLdrStrInstrTypeMask) == kLdrRegFpNegOffsetPattern);
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}
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bool Assembler::IsLdrPcImmediateOffset(Instr instr) {
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// Check the instruction is indeed a
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// ldr<cond> <Rd>, [pc +/- offset_12].
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return (instr & (kLdrPCMask & ~kCondMask)) == 0x051f0000;
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}
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|
|
|
bool Assembler::IsTstImmediate(Instr instr) {
|
|
return (instr & (B27 | B26 | I | kOpCodeMask | S | kRdMask)) ==
|
|
(I | TST | S);
|
|
}
|
|
|
|
|
|
bool Assembler::IsCmpRegister(Instr instr) {
|
|
return (instr & (B27 | B26 | I | kOpCodeMask | S | kRdMask | B4)) ==
|
|
(CMP | S);
|
|
}
|
|
|
|
|
|
bool Assembler::IsCmpImmediate(Instr instr) {
|
|
return (instr & (B27 | B26 | I | kOpCodeMask | S | kRdMask)) ==
|
|
(I | CMP | S);
|
|
}
|
|
|
|
|
|
Register Assembler::GetCmpImmediateRegister(Instr instr) {
|
|
ASSERT(IsCmpImmediate(instr));
|
|
return GetRn(instr);
|
|
}
|
|
|
|
|
|
int Assembler::GetCmpImmediateRawImmediate(Instr instr) {
|
|
ASSERT(IsCmpImmediate(instr));
|
|
return instr & kOff12Mask;
|
|
}
|
|
|
|
// Labels refer to positions in the (to be) generated code.
|
|
// There are bound, linked, and unused labels.
|
|
//
|
|
// Bound labels refer to known positions in the already
|
|
// generated code. pos() is the position the label refers to.
|
|
//
|
|
// Linked labels refer to unknown positions in the code
|
|
// to be generated; pos() is the position of the last
|
|
// instruction using the label.
|
|
|
|
|
|
// The link chain is terminated by a negative code position (must be aligned)
|
|
const int kEndOfChain = -4;
|
|
|
|
|
|
int Assembler::target_at(int pos) {
|
|
Instr instr = instr_at(pos);
|
|
if ((instr & ~kImm24Mask) == 0) {
|
|
// Emitted label constant, not part of a branch.
|
|
return instr - (Code::kHeaderSize - kHeapObjectTag);
|
|
}
|
|
ASSERT((instr & 7*B25) == 5*B25); // b, bl, or blx imm24
|
|
int imm26 = ((instr & kImm24Mask) << 8) >> 6;
|
|
if ((Instruction::ConditionField(instr) == kSpecialCondition) &&
|
|
((instr & B24) != 0)) {
|
|
// blx uses bit 24 to encode bit 2 of imm26
|
|
imm26 += 2;
|
|
}
|
|
return pos + kPcLoadDelta + imm26;
|
|
}
|
|
|
|
|
|
void Assembler::target_at_put(int pos, int target_pos) {
|
|
Instr instr = instr_at(pos);
|
|
if ((instr & ~kImm24Mask) == 0) {
|
|
ASSERT(target_pos == kEndOfChain || target_pos >= 0);
|
|
// Emitted label constant, not part of a branch.
|
|
// Make label relative to Code* of generated Code object.
|
|
instr_at_put(pos, target_pos + (Code::kHeaderSize - kHeapObjectTag));
|
|
return;
|
|
}
|
|
int imm26 = target_pos - (pos + kPcLoadDelta);
|
|
ASSERT((instr & 7*B25) == 5*B25); // b, bl, or blx imm24
|
|
if (Instruction::ConditionField(instr) == kSpecialCondition) {
|
|
// blx uses bit 24 to encode bit 2 of imm26
|
|
ASSERT((imm26 & 1) == 0);
|
|
instr = (instr & ~(B24 | kImm24Mask)) | ((imm26 & 2) >> 1)*B24;
|
|
} else {
|
|
ASSERT((imm26 & 3) == 0);
|
|
instr &= ~kImm24Mask;
|
|
}
|
|
int imm24 = imm26 >> 2;
|
|
ASSERT(is_int24(imm24));
|
|
instr_at_put(pos, instr | (imm24 & kImm24Mask));
|
|
}
|
|
|
|
|
|
void Assembler::print(Label* L) {
|
|
if (L->is_unused()) {
|
|
PrintF("unused label\n");
|
|
} else if (L->is_bound()) {
|
|
PrintF("bound label to %d\n", L->pos());
|
|
} else if (L->is_linked()) {
|
|
Label l = *L;
|
|
PrintF("unbound label");
|
|
while (l.is_linked()) {
|
|
PrintF("@ %d ", l.pos());
|
|
Instr instr = instr_at(l.pos());
|
|
if ((instr & ~kImm24Mask) == 0) {
|
|
PrintF("value\n");
|
|
} else {
|
|
ASSERT((instr & 7*B25) == 5*B25); // b, bl, or blx
|
|
Condition cond = Instruction::ConditionField(instr);
|
|
const char* b;
|
|
const char* c;
|
|
if (cond == kSpecialCondition) {
|
|
b = "blx";
|
|
c = "";
|
|
} else {
|
|
if ((instr & B24) != 0)
|
|
b = "bl";
|
|
else
|
|
b = "b";
|
|
|
|
switch (cond) {
|
|
case eq: c = "eq"; break;
|
|
case ne: c = "ne"; break;
|
|
case hs: c = "hs"; break;
|
|
case lo: c = "lo"; break;
|
|
case mi: c = "mi"; break;
|
|
case pl: c = "pl"; break;
|
|
case vs: c = "vs"; break;
|
|
case vc: c = "vc"; break;
|
|
case hi: c = "hi"; break;
|
|
case ls: c = "ls"; break;
|
|
case ge: c = "ge"; break;
|
|
case lt: c = "lt"; break;
|
|
case gt: c = "gt"; break;
|
|
case le: c = "le"; break;
|
|
case al: c = ""; break;
|
|
default:
|
|
c = "";
|
|
UNREACHABLE();
|
|
}
|
|
}
|
|
PrintF("%s%s\n", b, c);
|
|
}
|
|
next(&l);
|
|
}
|
|
} else {
|
|
PrintF("label in inconsistent state (pos = %d)\n", L->pos_);
|
|
}
|
|
}
|
|
|
|
|
|
void Assembler::bind_to(Label* L, int pos) {
|
|
ASSERT(0 <= pos && pos <= pc_offset()); // must have a valid binding position
|
|
while (L->is_linked()) {
|
|
int fixup_pos = L->pos();
|
|
next(L); // call next before overwriting link with target at fixup_pos
|
|
target_at_put(fixup_pos, pos);
|
|
}
|
|
L->bind_to(pos);
|
|
|
|
// Keep track of the last bound label so we don't eliminate any instructions
|
|
// before a bound label.
|
|
if (pos > last_bound_pos_)
|
|
last_bound_pos_ = pos;
|
|
}
|
|
|
|
|
|
void Assembler::link_to(Label* L, Label* appendix) {
|
|
if (appendix->is_linked()) {
|
|
if (L->is_linked()) {
|
|
// Append appendix to L's list.
|
|
int fixup_pos;
|
|
int link = L->pos();
|
|
do {
|
|
fixup_pos = link;
|
|
link = target_at(fixup_pos);
|
|
} while (link > 0);
|
|
ASSERT(link == kEndOfChain);
|
|
target_at_put(fixup_pos, appendix->pos());
|
|
} else {
|
|
// L is empty, simply use appendix.
|
|
*L = *appendix;
|
|
}
|
|
}
|
|
appendix->Unuse(); // appendix should not be used anymore
|
|
}
|
|
|
|
|
|
void Assembler::bind(Label* L) {
|
|
ASSERT(!L->is_bound()); // label can only be bound once
|
|
bind_to(L, pc_offset());
|
|
}
|
|
|
|
|
|
void Assembler::next(Label* L) {
|
|
ASSERT(L->is_linked());
|
|
int link = target_at(L->pos());
|
|
if (link == kEndOfChain) {
|
|
L->Unuse();
|
|
} else {
|
|
ASSERT(link >= 0);
|
|
L->link_to(link);
|
|
}
|
|
}
|
|
|
|
|
|
static Instr EncodeMovwImmediate(uint32_t immediate) {
|
|
ASSERT(immediate < 0x10000);
|
|
return ((immediate & 0xf000) << 4) | (immediate & 0xfff);
|
|
}
|
|
|
|
|
|
// Low-level code emission routines depending on the addressing mode.
|
|
// If this returns true then you have to use the rotate_imm and immed_8
|
|
// that it returns, because it may have already changed the instruction
|
|
// to match them!
|
|
static bool fits_shifter(uint32_t imm32,
|
|
uint32_t* rotate_imm,
|
|
uint32_t* immed_8,
|
|
Instr* instr) {
|
|
// imm32 must be unsigned.
|
|
for (int rot = 0; rot < 16; rot++) {
|
|
uint32_t imm8 = (imm32 << 2*rot) | (imm32 >> (32 - 2*rot));
|
|
if ((imm8 <= 0xff)) {
|
|
*rotate_imm = rot;
|
|
*immed_8 = imm8;
|
|
return true;
|
|
}
|
|
}
|
|
// If the opcode is one with a complementary version and the complementary
|
|
// immediate fits, change the opcode.
|
|
if (instr != NULL) {
|
|
if ((*instr & kMovMvnMask) == kMovMvnPattern) {
|
|
if (fits_shifter(~imm32, rotate_imm, immed_8, NULL)) {
|
|
*instr ^= kMovMvnFlip;
|
|
return true;
|
|
} else if ((*instr & kMovLeaveCCMask) == kMovLeaveCCPattern) {
|
|
if (CpuFeatures::IsSupported(ARMv7)) {
|
|
if (imm32 < 0x10000) {
|
|
*instr ^= kMovwLeaveCCFlip;
|
|
*instr |= EncodeMovwImmediate(imm32);
|
|
*rotate_imm = *immed_8 = 0; // Not used for movw.
|
|
return true;
|
|
}
|
|
}
|
|
}
|
|
} else if ((*instr & kCmpCmnMask) == kCmpCmnPattern) {
|
|
if (fits_shifter(-imm32, rotate_imm, immed_8, NULL)) {
|
|
*instr ^= kCmpCmnFlip;
|
|
return true;
|
|
}
|
|
} else {
|
|
Instr alu_insn = (*instr & kALUMask);
|
|
if (alu_insn == ADD ||
|
|
alu_insn == SUB) {
|
|
if (fits_shifter(-imm32, rotate_imm, immed_8, NULL)) {
|
|
*instr ^= kAddSubFlip;
|
|
return true;
|
|
}
|
|
} else if (alu_insn == AND ||
|
|
alu_insn == BIC) {
|
|
if (fits_shifter(~imm32, rotate_imm, immed_8, NULL)) {
|
|
*instr ^= kAndBicFlip;
|
|
return true;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
return false;
|
|
}
|
|
|
|
|
|
// We have to use the temporary register for things that can be relocated even
|
|
// if they can be encoded in the ARM's 12 bits of immediate-offset instruction
|
|
// space. There is no guarantee that the relocated location can be similarly
|
|
// encoded.
|
|
bool Operand::must_use_constant_pool() const {
|
|
if (rmode_ == RelocInfo::EXTERNAL_REFERENCE) {
|
|
#ifdef DEBUG
|
|
if (!Serializer::enabled()) {
|
|
Serializer::TooLateToEnableNow();
|
|
}
|
|
#endif // def DEBUG
|
|
return Serializer::enabled();
|
|
} else if (rmode_ == RelocInfo::NONE) {
|
|
return false;
|
|
}
|
|
return true;
|
|
}
|
|
|
|
|
|
bool Operand::is_single_instruction(Instr instr) const {
|
|
if (rm_.is_valid()) return true;
|
|
uint32_t dummy1, dummy2;
|
|
if (must_use_constant_pool() ||
|
|
!fits_shifter(imm32_, &dummy1, &dummy2, &instr)) {
|
|
// The immediate operand cannot be encoded as a shifter operand, or use of
|
|
// constant pool is required. For a mov instruction not setting the
|
|
// condition code additional instruction conventions can be used.
|
|
if ((instr & ~kCondMask) == 13*B21) { // mov, S not set
|
|
if (must_use_constant_pool() ||
|
|
!CpuFeatures::IsSupported(ARMv7)) {
|
|
// mov instruction will be an ldr from constant pool (one instruction).
|
|
return true;
|
|
} else {
|
|
// mov instruction will be a mov or movw followed by movt (two
|
|
// instructions).
|
|
return false;
|
|
}
|
|
} else {
|
|
// If this is not a mov or mvn instruction there will always an additional
|
|
// instructions - either mov or ldr. The mov might actually be two
|
|
// instructions mov or movw followed by movt so including the actual
|
|
// instruction two or three instructions will be generated.
|
|
return false;
|
|
}
|
|
} else {
|
|
// No use of constant pool and the immediate operand can be encoded as a
|
|
// shifter operand.
|
|
return true;
|
|
}
|
|
}
|
|
|
|
|
|
void Assembler::addrmod1(Instr instr,
|
|
Register rn,
|
|
Register rd,
|
|
const Operand& x) {
|
|
CheckBuffer();
|
|
ASSERT((instr & ~(kCondMask | kOpCodeMask | S)) == 0);
|
|
if (!x.rm_.is_valid()) {
|
|
// Immediate.
|
|
uint32_t rotate_imm;
|
|
uint32_t immed_8;
|
|
if (x.must_use_constant_pool() ||
|
|
!fits_shifter(x.imm32_, &rotate_imm, &immed_8, &instr)) {
|
|
// The immediate operand cannot be encoded as a shifter operand, so load
|
|
// it first to register ip and change the original instruction to use ip.
|
|
// However, if the original instruction is a 'mov rd, x' (not setting the
|
|
// condition code), then replace it with a 'ldr rd, [pc]'.
|
|
CHECK(!rn.is(ip)); // rn should never be ip, or will be trashed
|
|
Condition cond = Instruction::ConditionField(instr);
|
|
if ((instr & ~kCondMask) == 13*B21) { // mov, S not set
|
|
if (x.must_use_constant_pool() ||
|
|
!CpuFeatures::IsSupported(ARMv7)) {
|
|
RecordRelocInfo(x.rmode_, x.imm32_);
|
|
ldr(rd, MemOperand(pc, 0), cond);
|
|
} else {
|
|
// Will probably use movw, will certainly not use constant pool.
|
|
mov(rd, Operand(x.imm32_ & 0xffff), LeaveCC, cond);
|
|
movt(rd, static_cast<uint32_t>(x.imm32_) >> 16, cond);
|
|
}
|
|
} else {
|
|
// If this is not a mov or mvn instruction we may still be able to avoid
|
|
// a constant pool entry by using mvn or movw.
|
|
if (!x.must_use_constant_pool() &&
|
|
(instr & kMovMvnMask) != kMovMvnPattern) {
|
|
mov(ip, x, LeaveCC, cond);
|
|
} else {
|
|
RecordRelocInfo(x.rmode_, x.imm32_);
|
|
ldr(ip, MemOperand(pc, 0), cond);
|
|
}
|
|
addrmod1(instr, rn, rd, Operand(ip));
|
|
}
|
|
return;
|
|
}
|
|
instr |= I | rotate_imm*B8 | immed_8;
|
|
} else if (!x.rs_.is_valid()) {
|
|
// Immediate shift.
|
|
instr |= x.shift_imm_*B7 | x.shift_op_ | x.rm_.code();
|
|
} else {
|
|
// Register shift.
|
|
ASSERT(!rn.is(pc) && !rd.is(pc) && !x.rm_.is(pc) && !x.rs_.is(pc));
|
|
instr |= x.rs_.code()*B8 | x.shift_op_ | B4 | x.rm_.code();
|
|
}
|
|
emit(instr | rn.code()*B16 | rd.code()*B12);
|
|
if (rn.is(pc) || x.rm_.is(pc)) {
|
|
// Block constant pool emission for one instruction after reading pc.
|
|
BlockConstPoolFor(1);
|
|
}
|
|
}
|
|
|
|
|
|
void Assembler::addrmod2(Instr instr, Register rd, const MemOperand& x) {
|
|
ASSERT((instr & ~(kCondMask | B | L)) == B26);
|
|
int am = x.am_;
|
|
if (!x.rm_.is_valid()) {
|
|
// Immediate offset.
|
|
int offset_12 = x.offset_;
|
|
if (offset_12 < 0) {
|
|
offset_12 = -offset_12;
|
|
am ^= U;
|
|
}
|
|
if (!is_uint12(offset_12)) {
|
|
// Immediate offset cannot be encoded, load it first to register ip
|
|
// rn (and rd in a load) should never be ip, or will be trashed.
|
|
ASSERT(!x.rn_.is(ip) && ((instr & L) == L || !rd.is(ip)));
|
|
mov(ip, Operand(x.offset_), LeaveCC, Instruction::ConditionField(instr));
|
|
addrmod2(instr, rd, MemOperand(x.rn_, ip, x.am_));
|
|
return;
|
|
}
|
|
ASSERT(offset_12 >= 0); // no masking needed
|
|
instr |= offset_12;
|
|
} else {
|
|
// Register offset (shift_imm_ and shift_op_ are 0) or scaled
|
|
// register offset the constructors make sure than both shift_imm_
|
|
// and shift_op_ are initialized.
|
|
ASSERT(!x.rm_.is(pc));
|
|
instr |= B25 | x.shift_imm_*B7 | x.shift_op_ | x.rm_.code();
|
|
}
|
|
ASSERT((am & (P|W)) == P || !x.rn_.is(pc)); // no pc base with writeback
|
|
emit(instr | am | x.rn_.code()*B16 | rd.code()*B12);
|
|
}
|
|
|
|
|
|
void Assembler::addrmod3(Instr instr, Register rd, const MemOperand& x) {
|
|
ASSERT((instr & ~(kCondMask | L | S6 | H)) == (B4 | B7));
|
|
ASSERT(x.rn_.is_valid());
|
|
int am = x.am_;
|
|
if (!x.rm_.is_valid()) {
|
|
// Immediate offset.
|
|
int offset_8 = x.offset_;
|
|
if (offset_8 < 0) {
|
|
offset_8 = -offset_8;
|
|
am ^= U;
|
|
}
|
|
if (!is_uint8(offset_8)) {
|
|
// Immediate offset cannot be encoded, load it first to register ip
|
|
// rn (and rd in a load) should never be ip, or will be trashed.
|
|
ASSERT(!x.rn_.is(ip) && ((instr & L) == L || !rd.is(ip)));
|
|
mov(ip, Operand(x.offset_), LeaveCC, Instruction::ConditionField(instr));
|
|
addrmod3(instr, rd, MemOperand(x.rn_, ip, x.am_));
|
|
return;
|
|
}
|
|
ASSERT(offset_8 >= 0); // no masking needed
|
|
instr |= B | (offset_8 >> 4)*B8 | (offset_8 & 0xf);
|
|
} else if (x.shift_imm_ != 0) {
|
|
// Scaled register offset not supported, load index first
|
|
// rn (and rd in a load) should never be ip, or will be trashed.
|
|
ASSERT(!x.rn_.is(ip) && ((instr & L) == L || !rd.is(ip)));
|
|
mov(ip, Operand(x.rm_, x.shift_op_, x.shift_imm_), LeaveCC,
|
|
Instruction::ConditionField(instr));
|
|
addrmod3(instr, rd, MemOperand(x.rn_, ip, x.am_));
|
|
return;
|
|
} else {
|
|
// Register offset.
|
|
ASSERT((am & (P|W)) == P || !x.rm_.is(pc)); // no pc index with writeback
|
|
instr |= x.rm_.code();
|
|
}
|
|
ASSERT((am & (P|W)) == P || !x.rn_.is(pc)); // no pc base with writeback
|
|
emit(instr | am | x.rn_.code()*B16 | rd.code()*B12);
|
|
}
|
|
|
|
|
|
void Assembler::addrmod4(Instr instr, Register rn, RegList rl) {
|
|
ASSERT((instr & ~(kCondMask | P | U | W | L)) == B27);
|
|
ASSERT(rl != 0);
|
|
ASSERT(!rn.is(pc));
|
|
emit(instr | rn.code()*B16 | rl);
|
|
}
|
|
|
|
|
|
void Assembler::addrmod5(Instr instr, CRegister crd, const MemOperand& x) {
|
|
// Unindexed addressing is not encoded by this function.
|
|
ASSERT_EQ((B27 | B26),
|
|
(instr & ~(kCondMask | kCoprocessorMask | P | U | N | W | L)));
|
|
ASSERT(x.rn_.is_valid() && !x.rm_.is_valid());
|
|
int am = x.am_;
|
|
int offset_8 = x.offset_;
|
|
ASSERT((offset_8 & 3) == 0); // offset must be an aligned word offset
|
|
offset_8 >>= 2;
|
|
if (offset_8 < 0) {
|
|
offset_8 = -offset_8;
|
|
am ^= U;
|
|
}
|
|
ASSERT(is_uint8(offset_8)); // unsigned word offset must fit in a byte
|
|
ASSERT((am & (P|W)) == P || !x.rn_.is(pc)); // no pc base with writeback
|
|
|
|
// Post-indexed addressing requires W == 1; different than in addrmod2/3.
|
|
if ((am & P) == 0)
|
|
am |= W;
|
|
|
|
ASSERT(offset_8 >= 0); // no masking needed
|
|
emit(instr | am | x.rn_.code()*B16 | crd.code()*B12 | offset_8);
|
|
}
|
|
|
|
|
|
int Assembler::branch_offset(Label* L, bool jump_elimination_allowed) {
|
|
int target_pos;
|
|
if (L->is_bound()) {
|
|
target_pos = L->pos();
|
|
} else {
|
|
if (L->is_linked()) {
|
|
target_pos = L->pos(); // L's link
|
|
} else {
|
|
target_pos = kEndOfChain;
|
|
}
|
|
L->link_to(pc_offset());
|
|
}
|
|
|
|
// Block the emission of the constant pool, since the branch instruction must
|
|
// be emitted at the pc offset recorded by the label.
|
|
BlockConstPoolFor(1);
|
|
return target_pos - (pc_offset() + kPcLoadDelta);
|
|
}
|
|
|
|
|
|
void Assembler::label_at_put(Label* L, int at_offset) {
|
|
int target_pos;
|
|
if (L->is_bound()) {
|
|
target_pos = L->pos();
|
|
} else {
|
|
if (L->is_linked()) {
|
|
target_pos = L->pos(); // L's link
|
|
} else {
|
|
target_pos = kEndOfChain;
|
|
}
|
|
L->link_to(at_offset);
|
|
instr_at_put(at_offset, target_pos + (Code::kHeaderSize - kHeapObjectTag));
|
|
}
|
|
}
|
|
|
|
|
|
// Branch instructions.
|
|
void Assembler::b(int branch_offset, Condition cond) {
|
|
ASSERT((branch_offset & 3) == 0);
|
|
int imm24 = branch_offset >> 2;
|
|
ASSERT(is_int24(imm24));
|
|
emit(cond | B27 | B25 | (imm24 & kImm24Mask));
|
|
|
|
if (cond == al) {
|
|
// Dead code is a good location to emit the constant pool.
|
|
CheckConstPool(false, false);
|
|
}
|
|
}
|
|
|
|
|
|
void Assembler::bl(int branch_offset, Condition cond) {
|
|
positions_recorder()->WriteRecordedPositions();
|
|
ASSERT((branch_offset & 3) == 0);
|
|
int imm24 = branch_offset >> 2;
|
|
ASSERT(is_int24(imm24));
|
|
emit(cond | B27 | B25 | B24 | (imm24 & kImm24Mask));
|
|
}
|
|
|
|
|
|
void Assembler::blx(int branch_offset) { // v5 and above
|
|
positions_recorder()->WriteRecordedPositions();
|
|
ASSERT((branch_offset & 1) == 0);
|
|
int h = ((branch_offset & 2) >> 1)*B24;
|
|
int imm24 = branch_offset >> 2;
|
|
ASSERT(is_int24(imm24));
|
|
emit(kSpecialCondition | B27 | B25 | h | (imm24 & kImm24Mask));
|
|
}
|
|
|
|
|
|
void Assembler::blx(Register target, Condition cond) { // v5 and above
|
|
positions_recorder()->WriteRecordedPositions();
|
|
ASSERT(!target.is(pc));
|
|
emit(cond | B24 | B21 | 15*B16 | 15*B12 | 15*B8 | BLX | target.code());
|
|
}
|
|
|
|
|
|
void Assembler::bx(Register target, Condition cond) { // v5 and above, plus v4t
|
|
positions_recorder()->WriteRecordedPositions();
|
|
ASSERT(!target.is(pc)); // use of pc is actually allowed, but discouraged
|
|
emit(cond | B24 | B21 | 15*B16 | 15*B12 | 15*B8 | BX | target.code());
|
|
}
|
|
|
|
|
|
// Data-processing instructions.
|
|
|
|
void Assembler::and_(Register dst, Register src1, const Operand& src2,
|
|
SBit s, Condition cond) {
|
|
addrmod1(cond | AND | s, src1, dst, src2);
|
|
}
|
|
|
|
|
|
void Assembler::eor(Register dst, Register src1, const Operand& src2,
|
|
SBit s, Condition cond) {
|
|
addrmod1(cond | EOR | s, src1, dst, src2);
|
|
}
|
|
|
|
|
|
void Assembler::sub(Register dst, Register src1, const Operand& src2,
|
|
SBit s, Condition cond) {
|
|
addrmod1(cond | SUB | s, src1, dst, src2);
|
|
}
|
|
|
|
|
|
void Assembler::rsb(Register dst, Register src1, const Operand& src2,
|
|
SBit s, Condition cond) {
|
|
addrmod1(cond | RSB | s, src1, dst, src2);
|
|
}
|
|
|
|
|
|
void Assembler::add(Register dst, Register src1, const Operand& src2,
|
|
SBit s, Condition cond) {
|
|
addrmod1(cond | ADD | s, src1, dst, src2);
|
|
}
|
|
|
|
|
|
void Assembler::adc(Register dst, Register src1, const Operand& src2,
|
|
SBit s, Condition cond) {
|
|
addrmod1(cond | ADC | s, src1, dst, src2);
|
|
}
|
|
|
|
|
|
void Assembler::sbc(Register dst, Register src1, const Operand& src2,
|
|
SBit s, Condition cond) {
|
|
addrmod1(cond | SBC | s, src1, dst, src2);
|
|
}
|
|
|
|
|
|
void Assembler::rsc(Register dst, Register src1, const Operand& src2,
|
|
SBit s, Condition cond) {
|
|
addrmod1(cond | RSC | s, src1, dst, src2);
|
|
}
|
|
|
|
|
|
void Assembler::tst(Register src1, const Operand& src2, Condition cond) {
|
|
addrmod1(cond | TST | S, src1, r0, src2);
|
|
}
|
|
|
|
|
|
void Assembler::teq(Register src1, const Operand& src2, Condition cond) {
|
|
addrmod1(cond | TEQ | S, src1, r0, src2);
|
|
}
|
|
|
|
|
|
void Assembler::cmp(Register src1, const Operand& src2, Condition cond) {
|
|
addrmod1(cond | CMP | S, src1, r0, src2);
|
|
}
|
|
|
|
|
|
void Assembler::cmp_raw_immediate(
|
|
Register src, int raw_immediate, Condition cond) {
|
|
ASSERT(is_uint12(raw_immediate));
|
|
emit(cond | I | CMP | S | src.code() << 16 | raw_immediate);
|
|
}
|
|
|
|
|
|
void Assembler::cmn(Register src1, const Operand& src2, Condition cond) {
|
|
addrmod1(cond | CMN | S, src1, r0, src2);
|
|
}
|
|
|
|
|
|
void Assembler::orr(Register dst, Register src1, const Operand& src2,
|
|
SBit s, Condition cond) {
|
|
addrmod1(cond | ORR | s, src1, dst, src2);
|
|
}
|
|
|
|
|
|
void Assembler::mov(Register dst, const Operand& src, SBit s, Condition cond) {
|
|
if (dst.is(pc)) {
|
|
positions_recorder()->WriteRecordedPositions();
|
|
}
|
|
// Don't allow nop instructions in the form mov rn, rn to be generated using
|
|
// the mov instruction. They must be generated using nop(int/NopMarkerTypes)
|
|
// or MarkCode(int/NopMarkerTypes) pseudo instructions.
|
|
ASSERT(!(src.is_reg() && src.rm().is(dst) && s == LeaveCC && cond == al));
|
|
addrmod1(cond | MOV | s, r0, dst, src);
|
|
}
|
|
|
|
|
|
void Assembler::movw(Register reg, uint32_t immediate, Condition cond) {
|
|
ASSERT(immediate < 0x10000);
|
|
mov(reg, Operand(immediate), LeaveCC, cond);
|
|
}
|
|
|
|
|
|
void Assembler::movt(Register reg, uint32_t immediate, Condition cond) {
|
|
emit(cond | 0x34*B20 | reg.code()*B12 | EncodeMovwImmediate(immediate));
|
|
}
|
|
|
|
|
|
void Assembler::bic(Register dst, Register src1, const Operand& src2,
|
|
SBit s, Condition cond) {
|
|
addrmod1(cond | BIC | s, src1, dst, src2);
|
|
}
|
|
|
|
|
|
void Assembler::mvn(Register dst, const Operand& src, SBit s, Condition cond) {
|
|
addrmod1(cond | MVN | s, r0, dst, src);
|
|
}
|
|
|
|
|
|
// Multiply instructions.
|
|
void Assembler::mla(Register dst, Register src1, Register src2, Register srcA,
|
|
SBit s, Condition cond) {
|
|
ASSERT(!dst.is(pc) && !src1.is(pc) && !src2.is(pc) && !srcA.is(pc));
|
|
emit(cond | A | s | dst.code()*B16 | srcA.code()*B12 |
|
|
src2.code()*B8 | B7 | B4 | src1.code());
|
|
}
|
|
|
|
|
|
void Assembler::mul(Register dst, Register src1, Register src2,
|
|
SBit s, Condition cond) {
|
|
ASSERT(!dst.is(pc) && !src1.is(pc) && !src2.is(pc));
|
|
// dst goes in bits 16-19 for this instruction!
|
|
emit(cond | s | dst.code()*B16 | src2.code()*B8 | B7 | B4 | src1.code());
|
|
}
|
|
|
|
|
|
void Assembler::smlal(Register dstL,
|
|
Register dstH,
|
|
Register src1,
|
|
Register src2,
|
|
SBit s,
|
|
Condition cond) {
|
|
ASSERT(!dstL.is(pc) && !dstH.is(pc) && !src1.is(pc) && !src2.is(pc));
|
|
ASSERT(!dstL.is(dstH));
|
|
emit(cond | B23 | B22 | A | s | dstH.code()*B16 | dstL.code()*B12 |
|
|
src2.code()*B8 | B7 | B4 | src1.code());
|
|
}
|
|
|
|
|
|
void Assembler::smull(Register dstL,
|
|
Register dstH,
|
|
Register src1,
|
|
Register src2,
|
|
SBit s,
|
|
Condition cond) {
|
|
ASSERT(!dstL.is(pc) && !dstH.is(pc) && !src1.is(pc) && !src2.is(pc));
|
|
ASSERT(!dstL.is(dstH));
|
|
emit(cond | B23 | B22 | s | dstH.code()*B16 | dstL.code()*B12 |
|
|
src2.code()*B8 | B7 | B4 | src1.code());
|
|
}
|
|
|
|
|
|
void Assembler::umlal(Register dstL,
|
|
Register dstH,
|
|
Register src1,
|
|
Register src2,
|
|
SBit s,
|
|
Condition cond) {
|
|
ASSERT(!dstL.is(pc) && !dstH.is(pc) && !src1.is(pc) && !src2.is(pc));
|
|
ASSERT(!dstL.is(dstH));
|
|
emit(cond | B23 | A | s | dstH.code()*B16 | dstL.code()*B12 |
|
|
src2.code()*B8 | B7 | B4 | src1.code());
|
|
}
|
|
|
|
|
|
void Assembler::umull(Register dstL,
|
|
Register dstH,
|
|
Register src1,
|
|
Register src2,
|
|
SBit s,
|
|
Condition cond) {
|
|
ASSERT(!dstL.is(pc) && !dstH.is(pc) && !src1.is(pc) && !src2.is(pc));
|
|
ASSERT(!dstL.is(dstH));
|
|
emit(cond | B23 | s | dstH.code()*B16 | dstL.code()*B12 |
|
|
src2.code()*B8 | B7 | B4 | src1.code());
|
|
}
|
|
|
|
|
|
// Miscellaneous arithmetic instructions.
|
|
void Assembler::clz(Register dst, Register src, Condition cond) {
|
|
// v5 and above.
|
|
ASSERT(!dst.is(pc) && !src.is(pc));
|
|
emit(cond | B24 | B22 | B21 | 15*B16 | dst.code()*B12 |
|
|
15*B8 | CLZ | src.code());
|
|
}
|
|
|
|
|
|
// Saturating instructions.
|
|
|
|
// Unsigned saturate.
|
|
void Assembler::usat(Register dst,
|
|
int satpos,
|
|
const Operand& src,
|
|
Condition cond) {
|
|
// v6 and above.
|
|
ASSERT(CpuFeatures::IsSupported(ARMv7));
|
|
ASSERT(!dst.is(pc) && !src.rm_.is(pc));
|
|
ASSERT((satpos >= 0) && (satpos <= 31));
|
|
ASSERT((src.shift_op_ == ASR) || (src.shift_op_ == LSL));
|
|
ASSERT(src.rs_.is(no_reg));
|
|
|
|
int sh = 0;
|
|
if (src.shift_op_ == ASR) {
|
|
sh = 1;
|
|
}
|
|
|
|
emit(cond | 0x6*B24 | 0xe*B20 | satpos*B16 | dst.code()*B12 |
|
|
src.shift_imm_*B7 | sh*B6 | 0x1*B4 | src.rm_.code());
|
|
}
|
|
|
|
|
|
// Bitfield manipulation instructions.
|
|
|
|
// Unsigned bit field extract.
|
|
// Extracts #width adjacent bits from position #lsb in a register, and
|
|
// writes them to the low bits of a destination register.
|
|
// ubfx dst, src, #lsb, #width
|
|
void Assembler::ubfx(Register dst,
|
|
Register src,
|
|
int lsb,
|
|
int width,
|
|
Condition cond) {
|
|
// v7 and above.
|
|
ASSERT(CpuFeatures::IsSupported(ARMv7));
|
|
ASSERT(!dst.is(pc) && !src.is(pc));
|
|
ASSERT((lsb >= 0) && (lsb <= 31));
|
|
ASSERT((width >= 1) && (width <= (32 - lsb)));
|
|
emit(cond | 0xf*B23 | B22 | B21 | (width - 1)*B16 | dst.code()*B12 |
|
|
lsb*B7 | B6 | B4 | src.code());
|
|
}
|
|
|
|
|
|
// Signed bit field extract.
|
|
// Extracts #width adjacent bits from position #lsb in a register, and
|
|
// writes them to the low bits of a destination register. The extracted
|
|
// value is sign extended to fill the destination register.
|
|
// sbfx dst, src, #lsb, #width
|
|
void Assembler::sbfx(Register dst,
|
|
Register src,
|
|
int lsb,
|
|
int width,
|
|
Condition cond) {
|
|
// v7 and above.
|
|
ASSERT(CpuFeatures::IsSupported(ARMv7));
|
|
ASSERT(!dst.is(pc) && !src.is(pc));
|
|
ASSERT((lsb >= 0) && (lsb <= 31));
|
|
ASSERT((width >= 1) && (width <= (32 - lsb)));
|
|
emit(cond | 0xf*B23 | B21 | (width - 1)*B16 | dst.code()*B12 |
|
|
lsb*B7 | B6 | B4 | src.code());
|
|
}
|
|
|
|
|
|
// Bit field clear.
|
|
// Sets #width adjacent bits at position #lsb in the destination register
|
|
// to zero, preserving the value of the other bits.
|
|
// bfc dst, #lsb, #width
|
|
void Assembler::bfc(Register dst, int lsb, int width, Condition cond) {
|
|
// v7 and above.
|
|
ASSERT(CpuFeatures::IsSupported(ARMv7));
|
|
ASSERT(!dst.is(pc));
|
|
ASSERT((lsb >= 0) && (lsb <= 31));
|
|
ASSERT((width >= 1) && (width <= (32 - lsb)));
|
|
int msb = lsb + width - 1;
|
|
emit(cond | 0x1f*B22 | msb*B16 | dst.code()*B12 | lsb*B7 | B4 | 0xf);
|
|
}
|
|
|
|
|
|
// Bit field insert.
|
|
// Inserts #width adjacent bits from the low bits of the source register
|
|
// into position #lsb of the destination register.
|
|
// bfi dst, src, #lsb, #width
|
|
void Assembler::bfi(Register dst,
|
|
Register src,
|
|
int lsb,
|
|
int width,
|
|
Condition cond) {
|
|
// v7 and above.
|
|
ASSERT(CpuFeatures::IsSupported(ARMv7));
|
|
ASSERT(!dst.is(pc) && !src.is(pc));
|
|
ASSERT((lsb >= 0) && (lsb <= 31));
|
|
ASSERT((width >= 1) && (width <= (32 - lsb)));
|
|
int msb = lsb + width - 1;
|
|
emit(cond | 0x1f*B22 | msb*B16 | dst.code()*B12 | lsb*B7 | B4 |
|
|
src.code());
|
|
}
|
|
|
|
|
|
// Status register access instructions.
|
|
void Assembler::mrs(Register dst, SRegister s, Condition cond) {
|
|
ASSERT(!dst.is(pc));
|
|
emit(cond | B24 | s | 15*B16 | dst.code()*B12);
|
|
}
|
|
|
|
|
|
void Assembler::msr(SRegisterFieldMask fields, const Operand& src,
|
|
Condition cond) {
|
|
ASSERT(fields >= B16 && fields < B20); // at least one field set
|
|
Instr instr;
|
|
if (!src.rm_.is_valid()) {
|
|
// Immediate.
|
|
uint32_t rotate_imm;
|
|
uint32_t immed_8;
|
|
if (src.must_use_constant_pool() ||
|
|
!fits_shifter(src.imm32_, &rotate_imm, &immed_8, NULL)) {
|
|
// Immediate operand cannot be encoded, load it first to register ip.
|
|
RecordRelocInfo(src.rmode_, src.imm32_);
|
|
ldr(ip, MemOperand(pc, 0), cond);
|
|
msr(fields, Operand(ip), cond);
|
|
return;
|
|
}
|
|
instr = I | rotate_imm*B8 | immed_8;
|
|
} else {
|
|
ASSERT(!src.rs_.is_valid() && src.shift_imm_ == 0); // only rm allowed
|
|
instr = src.rm_.code();
|
|
}
|
|
emit(cond | instr | B24 | B21 | fields | 15*B12);
|
|
}
|
|
|
|
|
|
// Load/Store instructions.
|
|
void Assembler::ldr(Register dst, const MemOperand& src, Condition cond) {
|
|
if (dst.is(pc)) {
|
|
positions_recorder()->WriteRecordedPositions();
|
|
}
|
|
addrmod2(cond | B26 | L, dst, src);
|
|
}
|
|
|
|
|
|
void Assembler::str(Register src, const MemOperand& dst, Condition cond) {
|
|
addrmod2(cond | B26, src, dst);
|
|
}
|
|
|
|
|
|
void Assembler::ldrb(Register dst, const MemOperand& src, Condition cond) {
|
|
addrmod2(cond | B26 | B | L, dst, src);
|
|
}
|
|
|
|
|
|
void Assembler::strb(Register src, const MemOperand& dst, Condition cond) {
|
|
addrmod2(cond | B26 | B, src, dst);
|
|
}
|
|
|
|
|
|
void Assembler::ldrh(Register dst, const MemOperand& src, Condition cond) {
|
|
addrmod3(cond | L | B7 | H | B4, dst, src);
|
|
}
|
|
|
|
|
|
void Assembler::strh(Register src, const MemOperand& dst, Condition cond) {
|
|
addrmod3(cond | B7 | H | B4, src, dst);
|
|
}
|
|
|
|
|
|
void Assembler::ldrsb(Register dst, const MemOperand& src, Condition cond) {
|
|
addrmod3(cond | L | B7 | S6 | B4, dst, src);
|
|
}
|
|
|
|
|
|
void Assembler::ldrsh(Register dst, const MemOperand& src, Condition cond) {
|
|
addrmod3(cond | L | B7 | S6 | H | B4, dst, src);
|
|
}
|
|
|
|
|
|
void Assembler::ldrd(Register dst1, Register dst2,
|
|
const MemOperand& src, Condition cond) {
|
|
ASSERT(CpuFeatures::IsEnabled(ARMv7));
|
|
ASSERT(src.rm().is(no_reg));
|
|
ASSERT(!dst1.is(lr)); // r14.
|
|
ASSERT_EQ(0, dst1.code() % 2);
|
|
ASSERT_EQ(dst1.code() + 1, dst2.code());
|
|
addrmod3(cond | B7 | B6 | B4, dst1, src);
|
|
}
|
|
|
|
|
|
void Assembler::strd(Register src1, Register src2,
|
|
const MemOperand& dst, Condition cond) {
|
|
ASSERT(dst.rm().is(no_reg));
|
|
ASSERT(!src1.is(lr)); // r14.
|
|
ASSERT_EQ(0, src1.code() % 2);
|
|
ASSERT_EQ(src1.code() + 1, src2.code());
|
|
ASSERT(CpuFeatures::IsEnabled(ARMv7));
|
|
addrmod3(cond | B7 | B6 | B5 | B4, src1, dst);
|
|
}
|
|
|
|
// Load/Store multiple instructions.
|
|
void Assembler::ldm(BlockAddrMode am,
|
|
Register base,
|
|
RegList dst,
|
|
Condition cond) {
|
|
// ABI stack constraint: ldmxx base, {..sp..} base != sp is not restartable.
|
|
ASSERT(base.is(sp) || (dst & sp.bit()) == 0);
|
|
|
|
addrmod4(cond | B27 | am | L, base, dst);
|
|
|
|
// Emit the constant pool after a function return implemented by ldm ..{..pc}.
|
|
if (cond == al && (dst & pc.bit()) != 0) {
|
|
// There is a slight chance that the ldm instruction was actually a call,
|
|
// in which case it would be wrong to return into the constant pool; we
|
|
// recognize this case by checking if the emission of the pool was blocked
|
|
// at the pc of the ldm instruction by a mov lr, pc instruction; if this is
|
|
// the case, we emit a jump over the pool.
|
|
CheckConstPool(true, no_const_pool_before_ == pc_offset() - kInstrSize);
|
|
}
|
|
}
|
|
|
|
|
|
void Assembler::stm(BlockAddrMode am,
|
|
Register base,
|
|
RegList src,
|
|
Condition cond) {
|
|
addrmod4(cond | B27 | am, base, src);
|
|
}
|
|
|
|
|
|
// Exception-generating instructions and debugging support.
|
|
// Stops with a non-negative code less than kNumOfWatchedStops support
|
|
// enabling/disabling and a counter feature. See simulator-arm.h .
|
|
void Assembler::stop(const char* msg, Condition cond, int32_t code) {
|
|
#ifndef __arm__
|
|
ASSERT(code >= kDefaultStopCode);
|
|
{
|
|
// The Simulator will handle the stop instruction and get the message
|
|
// address. It expects to find the address just after the svc instruction.
|
|
BlockConstPoolScope block_const_pool(this);
|
|
if (code >= 0) {
|
|
svc(kStopCode + code, cond);
|
|
} else {
|
|
svc(kStopCode + kMaxStopCode, cond);
|
|
}
|
|
emit(reinterpret_cast<Instr>(msg));
|
|
}
|
|
#else // def __arm__
|
|
#ifdef CAN_USE_ARMV5_INSTRUCTIONS
|
|
if (cond != al) {
|
|
Label skip;
|
|
b(&skip, NegateCondition(cond));
|
|
bkpt(0);
|
|
bind(&skip);
|
|
} else {
|
|
bkpt(0);
|
|
}
|
|
#else // ndef CAN_USE_ARMV5_INSTRUCTIONS
|
|
svc(0x9f0001, cond);
|
|
#endif // ndef CAN_USE_ARMV5_INSTRUCTIONS
|
|
#endif // def __arm__
|
|
}
|
|
|
|
|
|
void Assembler::bkpt(uint32_t imm16) { // v5 and above
|
|
ASSERT(is_uint16(imm16));
|
|
emit(al | B24 | B21 | (imm16 >> 4)*B8 | BKPT | (imm16 & 0xf));
|
|
}
|
|
|
|
|
|
void Assembler::svc(uint32_t imm24, Condition cond) {
|
|
ASSERT(is_uint24(imm24));
|
|
emit(cond | 15*B24 | imm24);
|
|
}
|
|
|
|
|
|
// Coprocessor instructions.
|
|
void Assembler::cdp(Coprocessor coproc,
|
|
int opcode_1,
|
|
CRegister crd,
|
|
CRegister crn,
|
|
CRegister crm,
|
|
int opcode_2,
|
|
Condition cond) {
|
|
ASSERT(is_uint4(opcode_1) && is_uint3(opcode_2));
|
|
emit(cond | B27 | B26 | B25 | (opcode_1 & 15)*B20 | crn.code()*B16 |
|
|
crd.code()*B12 | coproc*B8 | (opcode_2 & 7)*B5 | crm.code());
|
|
}
|
|
|
|
|
|
void Assembler::cdp2(Coprocessor coproc,
|
|
int opcode_1,
|
|
CRegister crd,
|
|
CRegister crn,
|
|
CRegister crm,
|
|
int opcode_2) { // v5 and above
|
|
cdp(coproc, opcode_1, crd, crn, crm, opcode_2, kSpecialCondition);
|
|
}
|
|
|
|
|
|
void Assembler::mcr(Coprocessor coproc,
|
|
int opcode_1,
|
|
Register rd,
|
|
CRegister crn,
|
|
CRegister crm,
|
|
int opcode_2,
|
|
Condition cond) {
|
|
ASSERT(is_uint3(opcode_1) && is_uint3(opcode_2));
|
|
emit(cond | B27 | B26 | B25 | (opcode_1 & 7)*B21 | crn.code()*B16 |
|
|
rd.code()*B12 | coproc*B8 | (opcode_2 & 7)*B5 | B4 | crm.code());
|
|
}
|
|
|
|
|
|
void Assembler::mcr2(Coprocessor coproc,
|
|
int opcode_1,
|
|
Register rd,
|
|
CRegister crn,
|
|
CRegister crm,
|
|
int opcode_2) { // v5 and above
|
|
mcr(coproc, opcode_1, rd, crn, crm, opcode_2, kSpecialCondition);
|
|
}
|
|
|
|
|
|
void Assembler::mrc(Coprocessor coproc,
|
|
int opcode_1,
|
|
Register rd,
|
|
CRegister crn,
|
|
CRegister crm,
|
|
int opcode_2,
|
|
Condition cond) {
|
|
ASSERT(is_uint3(opcode_1) && is_uint3(opcode_2));
|
|
emit(cond | B27 | B26 | B25 | (opcode_1 & 7)*B21 | L | crn.code()*B16 |
|
|
rd.code()*B12 | coproc*B8 | (opcode_2 & 7)*B5 | B4 | crm.code());
|
|
}
|
|
|
|
|
|
void Assembler::mrc2(Coprocessor coproc,
|
|
int opcode_1,
|
|
Register rd,
|
|
CRegister crn,
|
|
CRegister crm,
|
|
int opcode_2) { // v5 and above
|
|
mrc(coproc, opcode_1, rd, crn, crm, opcode_2, kSpecialCondition);
|
|
}
|
|
|
|
|
|
void Assembler::ldc(Coprocessor coproc,
|
|
CRegister crd,
|
|
const MemOperand& src,
|
|
LFlag l,
|
|
Condition cond) {
|
|
addrmod5(cond | B27 | B26 | l | L | coproc*B8, crd, src);
|
|
}
|
|
|
|
|
|
void Assembler::ldc(Coprocessor coproc,
|
|
CRegister crd,
|
|
Register rn,
|
|
int option,
|
|
LFlag l,
|
|
Condition cond) {
|
|
// Unindexed addressing.
|
|
ASSERT(is_uint8(option));
|
|
emit(cond | B27 | B26 | U | l | L | rn.code()*B16 | crd.code()*B12 |
|
|
coproc*B8 | (option & 255));
|
|
}
|
|
|
|
|
|
void Assembler::ldc2(Coprocessor coproc,
|
|
CRegister crd,
|
|
const MemOperand& src,
|
|
LFlag l) { // v5 and above
|
|
ldc(coproc, crd, src, l, kSpecialCondition);
|
|
}
|
|
|
|
|
|
void Assembler::ldc2(Coprocessor coproc,
|
|
CRegister crd,
|
|
Register rn,
|
|
int option,
|
|
LFlag l) { // v5 and above
|
|
ldc(coproc, crd, rn, option, l, kSpecialCondition);
|
|
}
|
|
|
|
|
|
// Support for VFP.
|
|
|
|
void Assembler::vldr(const DwVfpRegister dst,
|
|
const Register base,
|
|
int offset,
|
|
const Condition cond) {
|
|
// Ddst = MEM(Rbase + offset).
|
|
// Instruction details available in ARM DDI 0406A, A8-628.
|
|
// cond(31-28) | 1101(27-24)| U001(23-20) | Rbase(19-16) |
|
|
// Vdst(15-12) | 1011(11-8) | offset
|
|
ASSERT(CpuFeatures::IsEnabled(VFP3));
|
|
int u = 1;
|
|
if (offset < 0) {
|
|
offset = -offset;
|
|
u = 0;
|
|
}
|
|
|
|
ASSERT(offset >= 0);
|
|
if ((offset % 4) == 0 && (offset / 4) < 256) {
|
|
emit(cond | u*B23 | 0xD1*B20 | base.code()*B16 | dst.code()*B12 |
|
|
0xB*B8 | ((offset / 4) & 255));
|
|
} else {
|
|
// Larger offsets must be handled by computing the correct address
|
|
// in the ip register.
|
|
ASSERT(!base.is(ip));
|
|
if (u == 1) {
|
|
add(ip, base, Operand(offset));
|
|
} else {
|
|
sub(ip, base, Operand(offset));
|
|
}
|
|
emit(cond | 0xD1*B20 | ip.code()*B16 | dst.code()*B12 | 0xB*B8);
|
|
}
|
|
}
|
|
|
|
|
|
void Assembler::vldr(const DwVfpRegister dst,
|
|
const MemOperand& operand,
|
|
const Condition cond) {
|
|
ASSERT(!operand.rm().is_valid());
|
|
ASSERT(operand.am_ == Offset);
|
|
vldr(dst, operand.rn(), operand.offset(), cond);
|
|
}
|
|
|
|
|
|
void Assembler::vldr(const SwVfpRegister dst,
|
|
const Register base,
|
|
int offset,
|
|
const Condition cond) {
|
|
// Sdst = MEM(Rbase + offset).
|
|
// Instruction details available in ARM DDI 0406A, A8-628.
|
|
// cond(31-28) | 1101(27-24)| U001(23-20) | Rbase(19-16) |
|
|
// Vdst(15-12) | 1010(11-8) | offset
|
|
ASSERT(CpuFeatures::IsEnabled(VFP3));
|
|
int u = 1;
|
|
if (offset < 0) {
|
|
offset = -offset;
|
|
u = 0;
|
|
}
|
|
int sd, d;
|
|
dst.split_code(&sd, &d);
|
|
ASSERT(offset >= 0);
|
|
|
|
if ((offset % 4) == 0 && (offset / 4) < 256) {
|
|
emit(cond | u*B23 | d*B22 | 0xD1*B20 | base.code()*B16 | sd*B12 |
|
|
0xA*B8 | ((offset / 4) & 255));
|
|
} else {
|
|
// Larger offsets must be handled by computing the correct address
|
|
// in the ip register.
|
|
ASSERT(!base.is(ip));
|
|
if (u == 1) {
|
|
add(ip, base, Operand(offset));
|
|
} else {
|
|
sub(ip, base, Operand(offset));
|
|
}
|
|
emit(cond | d*B22 | 0xD1*B20 | ip.code()*B16 | sd*B12 | 0xA*B8);
|
|
}
|
|
}
|
|
|
|
|
|
void Assembler::vldr(const SwVfpRegister dst,
|
|
const MemOperand& operand,
|
|
const Condition cond) {
|
|
ASSERT(!operand.rm().is_valid());
|
|
ASSERT(operand.am_ == Offset);
|
|
vldr(dst, operand.rn(), operand.offset(), cond);
|
|
}
|
|
|
|
|
|
void Assembler::vstr(const DwVfpRegister src,
|
|
const Register base,
|
|
int offset,
|
|
const Condition cond) {
|
|
// MEM(Rbase + offset) = Dsrc.
|
|
// Instruction details available in ARM DDI 0406A, A8-786.
|
|
// cond(31-28) | 1101(27-24)| U000(23-20) | | Rbase(19-16) |
|
|
// Vsrc(15-12) | 1011(11-8) | (offset/4)
|
|
ASSERT(CpuFeatures::IsEnabled(VFP3));
|
|
int u = 1;
|
|
if (offset < 0) {
|
|
offset = -offset;
|
|
u = 0;
|
|
}
|
|
ASSERT(offset >= 0);
|
|
if ((offset % 4) == 0 && (offset / 4) < 256) {
|
|
emit(cond | u*B23 | 0xD0*B20 | base.code()*B16 | src.code()*B12 |
|
|
0xB*B8 | ((offset / 4) & 255));
|
|
} else {
|
|
// Larger offsets must be handled by computing the correct address
|
|
// in the ip register.
|
|
ASSERT(!base.is(ip));
|
|
if (u == 1) {
|
|
add(ip, base, Operand(offset));
|
|
} else {
|
|
sub(ip, base, Operand(offset));
|
|
}
|
|
emit(cond | 0xD0*B20 | ip.code()*B16 | src.code()*B12 | 0xB*B8);
|
|
}
|
|
}
|
|
|
|
|
|
void Assembler::vstr(const DwVfpRegister src,
|
|
const MemOperand& operand,
|
|
const Condition cond) {
|
|
ASSERT(!operand.rm().is_valid());
|
|
ASSERT(operand.am_ == Offset);
|
|
vstr(src, operand.rn(), operand.offset(), cond);
|
|
}
|
|
|
|
|
|
void Assembler::vstr(const SwVfpRegister src,
|
|
const Register base,
|
|
int offset,
|
|
const Condition cond) {
|
|
// MEM(Rbase + offset) = SSrc.
|
|
// Instruction details available in ARM DDI 0406A, A8-786.
|
|
// cond(31-28) | 1101(27-24)| U000(23-20) | Rbase(19-16) |
|
|
// Vdst(15-12) | 1010(11-8) | (offset/4)
|
|
ASSERT(CpuFeatures::IsEnabled(VFP3));
|
|
int u = 1;
|
|
if (offset < 0) {
|
|
offset = -offset;
|
|
u = 0;
|
|
}
|
|
int sd, d;
|
|
src.split_code(&sd, &d);
|
|
ASSERT(offset >= 0);
|
|
if ((offset % 4) == 0 && (offset / 4) < 256) {
|
|
emit(cond | u*B23 | d*B22 | 0xD0*B20 | base.code()*B16 | sd*B12 |
|
|
0xA*B8 | ((offset / 4) & 255));
|
|
} else {
|
|
// Larger offsets must be handled by computing the correct address
|
|
// in the ip register.
|
|
ASSERT(!base.is(ip));
|
|
if (u == 1) {
|
|
add(ip, base, Operand(offset));
|
|
} else {
|
|
sub(ip, base, Operand(offset));
|
|
}
|
|
emit(cond | d*B22 | 0xD0*B20 | ip.code()*B16 | sd*B12 | 0xA*B8);
|
|
}
|
|
}
|
|
|
|
|
|
void Assembler::vstr(const SwVfpRegister src,
|
|
const MemOperand& operand,
|
|
const Condition cond) {
|
|
ASSERT(!operand.rm().is_valid());
|
|
ASSERT(operand.am_ == Offset);
|
|
vldr(src, operand.rn(), operand.offset(), cond);
|
|
}
|
|
|
|
|
|
void Assembler::vldm(BlockAddrMode am,
|
|
Register base,
|
|
DwVfpRegister first,
|
|
DwVfpRegister last,
|
|
Condition cond) {
|
|
// Instruction details available in ARM DDI 0406A, A8-626.
|
|
// cond(31-28) | 110(27-25)| PUDW1(24-20) | Rbase(19-16) |
|
|
// first(15-12) | 1010(11-8) | (count * 2)
|
|
ASSERT(CpuFeatures::IsEnabled(VFP3));
|
|
ASSERT_LE(first.code(), last.code());
|
|
ASSERT(am == ia || am == ia_w || am == db_w);
|
|
ASSERT(!base.is(pc));
|
|
|
|
int sd, d;
|
|
first.split_code(&sd, &d);
|
|
int count = last.code() - first.code() + 1;
|
|
emit(cond | B27 | B26 | am | d*B22 | B20 | base.code()*B16 | sd*B12 |
|
|
0xB*B8 | count*2);
|
|
}
|
|
|
|
|
|
void Assembler::vstm(BlockAddrMode am,
|
|
Register base,
|
|
DwVfpRegister first,
|
|
DwVfpRegister last,
|
|
Condition cond) {
|
|
// Instruction details available in ARM DDI 0406A, A8-784.
|
|
// cond(31-28) | 110(27-25)| PUDW0(24-20) | Rbase(19-16) |
|
|
// first(15-12) | 1011(11-8) | (count * 2)
|
|
ASSERT(CpuFeatures::IsEnabled(VFP3));
|
|
ASSERT_LE(first.code(), last.code());
|
|
ASSERT(am == ia || am == ia_w || am == db_w);
|
|
ASSERT(!base.is(pc));
|
|
|
|
int sd, d;
|
|
first.split_code(&sd, &d);
|
|
int count = last.code() - first.code() + 1;
|
|
emit(cond | B27 | B26 | am | d*B22 | base.code()*B16 | sd*B12 |
|
|
0xB*B8 | count*2);
|
|
}
|
|
|
|
void Assembler::vldm(BlockAddrMode am,
|
|
Register base,
|
|
SwVfpRegister first,
|
|
SwVfpRegister last,
|
|
Condition cond) {
|
|
// Instruction details available in ARM DDI 0406A, A8-626.
|
|
// cond(31-28) | 110(27-25)| PUDW1(24-20) | Rbase(19-16) |
|
|
// first(15-12) | 1010(11-8) | (count/2)
|
|
ASSERT(CpuFeatures::IsEnabled(VFP3));
|
|
ASSERT_LE(first.code(), last.code());
|
|
ASSERT(am == ia || am == ia_w || am == db_w);
|
|
ASSERT(!base.is(pc));
|
|
|
|
int sd, d;
|
|
first.split_code(&sd, &d);
|
|
int count = last.code() - first.code() + 1;
|
|
emit(cond | B27 | B26 | am | d*B22 | B20 | base.code()*B16 | sd*B12 |
|
|
0xA*B8 | count);
|
|
}
|
|
|
|
|
|
void Assembler::vstm(BlockAddrMode am,
|
|
Register base,
|
|
SwVfpRegister first,
|
|
SwVfpRegister last,
|
|
Condition cond) {
|
|
// Instruction details available in ARM DDI 0406A, A8-784.
|
|
// cond(31-28) | 110(27-25)| PUDW0(24-20) | Rbase(19-16) |
|
|
// first(15-12) | 1011(11-8) | (count/2)
|
|
ASSERT(CpuFeatures::IsEnabled(VFP3));
|
|
ASSERT_LE(first.code(), last.code());
|
|
ASSERT(am == ia || am == ia_w || am == db_w);
|
|
ASSERT(!base.is(pc));
|
|
|
|
int sd, d;
|
|
first.split_code(&sd, &d);
|
|
int count = last.code() - first.code() + 1;
|
|
emit(cond | B27 | B26 | am | d*B22 | base.code()*B16 | sd*B12 |
|
|
0xA*B8 | count);
|
|
}
|
|
|
|
static void DoubleAsTwoUInt32(double d, uint32_t* lo, uint32_t* hi) {
|
|
uint64_t i;
|
|
memcpy(&i, &d, 8);
|
|
|
|
*lo = i & 0xffffffff;
|
|
*hi = i >> 32;
|
|
}
|
|
|
|
// Only works for little endian floating point formats.
|
|
// We don't support VFP on the mixed endian floating point platform.
|
|
static bool FitsVMOVDoubleImmediate(double d, uint32_t *encoding) {
|
|
ASSERT(CpuFeatures::IsEnabled(VFP3));
|
|
|
|
// VMOV can accept an immediate of the form:
|
|
//
|
|
// +/- m * 2^(-n) where 16 <= m <= 31 and 0 <= n <= 7
|
|
//
|
|
// The immediate is encoded using an 8-bit quantity, comprised of two
|
|
// 4-bit fields. For an 8-bit immediate of the form:
|
|
//
|
|
// [abcdefgh]
|
|
//
|
|
// where a is the MSB and h is the LSB, an immediate 64-bit double can be
|
|
// created of the form:
|
|
//
|
|
// [aBbbbbbb,bbcdefgh,00000000,00000000,
|
|
// 00000000,00000000,00000000,00000000]
|
|
//
|
|
// where B = ~b.
|
|
//
|
|
|
|
uint32_t lo, hi;
|
|
DoubleAsTwoUInt32(d, &lo, &hi);
|
|
|
|
// The most obvious constraint is the long block of zeroes.
|
|
if ((lo != 0) || ((hi & 0xffff) != 0)) {
|
|
return false;
|
|
}
|
|
|
|
// Bits 62:55 must be all clear or all set.
|
|
if (((hi & 0x3fc00000) != 0) && ((hi & 0x3fc00000) != 0x3fc00000)) {
|
|
return false;
|
|
}
|
|
|
|
// Bit 63 must be NOT bit 62.
|
|
if (((hi ^ (hi << 1)) & (0x40000000)) == 0) {
|
|
return false;
|
|
}
|
|
|
|
// Create the encoded immediate in the form:
|
|
// [00000000,0000abcd,00000000,0000efgh]
|
|
*encoding = (hi >> 16) & 0xf; // Low nybble.
|
|
*encoding |= (hi >> 4) & 0x70000; // Low three bits of the high nybble.
|
|
*encoding |= (hi >> 12) & 0x80000; // Top bit of the high nybble.
|
|
|
|
return true;
|
|
}
|
|
|
|
|
|
void Assembler::vmov(const DwVfpRegister dst,
|
|
double imm,
|
|
const Condition cond) {
|
|
// Dd = immediate
|
|
// Instruction details available in ARM DDI 0406B, A8-640.
|
|
ASSERT(CpuFeatures::IsEnabled(VFP3));
|
|
|
|
uint32_t enc;
|
|
if (FitsVMOVDoubleImmediate(imm, &enc)) {
|
|
// The double can be encoded in the instruction.
|
|
emit(cond | 0xE*B24 | 0xB*B20 | dst.code()*B12 | 0xB*B8 | enc);
|
|
} else {
|
|
// Synthesise the double from ARM immediates. This could be implemented
|
|
// using vldr from a constant pool.
|
|
uint32_t lo, hi;
|
|
DoubleAsTwoUInt32(imm, &lo, &hi);
|
|
|
|
if (lo == hi) {
|
|
// If the lo and hi parts of the double are equal, the literal is easier
|
|
// to create. This is the case with 0.0.
|
|
mov(ip, Operand(lo));
|
|
vmov(dst, ip, ip);
|
|
} else {
|
|
// Move the low part of the double into the lower of the corresponsing S
|
|
// registers of D register dst.
|
|
mov(ip, Operand(lo));
|
|
vmov(dst.low(), ip, cond);
|
|
|
|
// Move the high part of the double into the higher of the corresponsing S
|
|
// registers of D register dst.
|
|
mov(ip, Operand(hi));
|
|
vmov(dst.high(), ip, cond);
|
|
}
|
|
}
|
|
}
|
|
|
|
|
|
void Assembler::vmov(const SwVfpRegister dst,
|
|
const SwVfpRegister src,
|
|
const Condition cond) {
|
|
// Sd = Sm
|
|
// Instruction details available in ARM DDI 0406B, A8-642.
|
|
ASSERT(CpuFeatures::IsEnabled(VFP3));
|
|
int sd, d, sm, m;
|
|
dst.split_code(&sd, &d);
|
|
src.split_code(&sm, &m);
|
|
emit(cond | 0xE*B24 | d*B22 | 0xB*B20 | sd*B12 | 0xA*B8 | B6 | m*B5 | sm);
|
|
}
|
|
|
|
|
|
void Assembler::vmov(const DwVfpRegister dst,
|
|
const DwVfpRegister src,
|
|
const Condition cond) {
|
|
// Dd = Dm
|
|
// Instruction details available in ARM DDI 0406B, A8-642.
|
|
ASSERT(CpuFeatures::IsEnabled(VFP3));
|
|
emit(cond | 0xE*B24 | 0xB*B20 |
|
|
dst.code()*B12 | 0x5*B9 | B8 | B6 | src.code());
|
|
}
|
|
|
|
|
|
void Assembler::vmov(const DwVfpRegister dst,
|
|
const Register src1,
|
|
const Register src2,
|
|
const Condition cond) {
|
|
// Dm = <Rt,Rt2>.
|
|
// Instruction details available in ARM DDI 0406A, A8-646.
|
|
// cond(31-28) | 1100(27-24)| 010(23-21) | op=0(20) | Rt2(19-16) |
|
|
// Rt(15-12) | 1011(11-8) | 00(7-6) | M(5) | 1(4) | Vm
|
|
ASSERT(CpuFeatures::IsEnabled(VFP3));
|
|
ASSERT(!src1.is(pc) && !src2.is(pc));
|
|
emit(cond | 0xC*B24 | B22 | src2.code()*B16 |
|
|
src1.code()*B12 | 0xB*B8 | B4 | dst.code());
|
|
}
|
|
|
|
|
|
void Assembler::vmov(const Register dst1,
|
|
const Register dst2,
|
|
const DwVfpRegister src,
|
|
const Condition cond) {
|
|
// <Rt,Rt2> = Dm.
|
|
// Instruction details available in ARM DDI 0406A, A8-646.
|
|
// cond(31-28) | 1100(27-24)| 010(23-21) | op=1(20) | Rt2(19-16) |
|
|
// Rt(15-12) | 1011(11-8) | 00(7-6) | M(5) | 1(4) | Vm
|
|
ASSERT(CpuFeatures::IsEnabled(VFP3));
|
|
ASSERT(!dst1.is(pc) && !dst2.is(pc));
|
|
emit(cond | 0xC*B24 | B22 | B20 | dst2.code()*B16 |
|
|
dst1.code()*B12 | 0xB*B8 | B4 | src.code());
|
|
}
|
|
|
|
|
|
void Assembler::vmov(const SwVfpRegister dst,
|
|
const Register src,
|
|
const Condition cond) {
|
|
// Sn = Rt.
|
|
// Instruction details available in ARM DDI 0406A, A8-642.
|
|
// cond(31-28) | 1110(27-24)| 000(23-21) | op=0(20) | Vn(19-16) |
|
|
// Rt(15-12) | 1010(11-8) | N(7)=0 | 00(6-5) | 1(4) | 0000(3-0)
|
|
ASSERT(CpuFeatures::IsEnabled(VFP3));
|
|
ASSERT(!src.is(pc));
|
|
int sn, n;
|
|
dst.split_code(&sn, &n);
|
|
emit(cond | 0xE*B24 | sn*B16 | src.code()*B12 | 0xA*B8 | n*B7 | B4);
|
|
}
|
|
|
|
|
|
void Assembler::vmov(const Register dst,
|
|
const SwVfpRegister src,
|
|
const Condition cond) {
|
|
// Rt = Sn.
|
|
// Instruction details available in ARM DDI 0406A, A8-642.
|
|
// cond(31-28) | 1110(27-24)| 000(23-21) | op=1(20) | Vn(19-16) |
|
|
// Rt(15-12) | 1010(11-8) | N(7)=0 | 00(6-5) | 1(4) | 0000(3-0)
|
|
ASSERT(CpuFeatures::IsEnabled(VFP3));
|
|
ASSERT(!dst.is(pc));
|
|
int sn, n;
|
|
src.split_code(&sn, &n);
|
|
emit(cond | 0xE*B24 | B20 | sn*B16 | dst.code()*B12 | 0xA*B8 | n*B7 | B4);
|
|
}
|
|
|
|
|
|
// Type of data to read from or write to VFP register.
|
|
// Used as specifier in generic vcvt instruction.
|
|
enum VFPType { S32, U32, F32, F64 };
|
|
|
|
|
|
static bool IsSignedVFPType(VFPType type) {
|
|
switch (type) {
|
|
case S32:
|
|
return true;
|
|
case U32:
|
|
return false;
|
|
default:
|
|
UNREACHABLE();
|
|
return false;
|
|
}
|
|
}
|
|
|
|
|
|
static bool IsIntegerVFPType(VFPType type) {
|
|
switch (type) {
|
|
case S32:
|
|
case U32:
|
|
return true;
|
|
case F32:
|
|
case F64:
|
|
return false;
|
|
default:
|
|
UNREACHABLE();
|
|
return false;
|
|
}
|
|
}
|
|
|
|
|
|
static bool IsDoubleVFPType(VFPType type) {
|
|
switch (type) {
|
|
case F32:
|
|
return false;
|
|
case F64:
|
|
return true;
|
|
default:
|
|
UNREACHABLE();
|
|
return false;
|
|
}
|
|
}
|
|
|
|
|
|
// Split five bit reg_code based on size of reg_type.
|
|
// 32-bit register codes are Vm:M
|
|
// 64-bit register codes are M:Vm
|
|
// where Vm is four bits, and M is a single bit.
|
|
static void SplitRegCode(VFPType reg_type,
|
|
int reg_code,
|
|
int* vm,
|
|
int* m) {
|
|
ASSERT((reg_code >= 0) && (reg_code <= 31));
|
|
if (IsIntegerVFPType(reg_type) || !IsDoubleVFPType(reg_type)) {
|
|
// 32 bit type.
|
|
*m = reg_code & 0x1;
|
|
*vm = reg_code >> 1;
|
|
} else {
|
|
// 64 bit type.
|
|
*m = (reg_code & 0x10) >> 4;
|
|
*vm = reg_code & 0x0F;
|
|
}
|
|
}
|
|
|
|
|
|
// Encode vcvt.src_type.dst_type instruction.
|
|
static Instr EncodeVCVT(const VFPType dst_type,
|
|
const int dst_code,
|
|
const VFPType src_type,
|
|
const int src_code,
|
|
VFPConversionMode mode,
|
|
const Condition cond) {
|
|
ASSERT(src_type != dst_type);
|
|
int D, Vd, M, Vm;
|
|
SplitRegCode(src_type, src_code, &Vm, &M);
|
|
SplitRegCode(dst_type, dst_code, &Vd, &D);
|
|
|
|
if (IsIntegerVFPType(dst_type) || IsIntegerVFPType(src_type)) {
|
|
// Conversion between IEEE floating point and 32-bit integer.
|
|
// Instruction details available in ARM DDI 0406B, A8.6.295.
|
|
// cond(31-28) | 11101(27-23)| D(22) | 11(21-20) | 1(19) | opc2(18-16) |
|
|
// Vd(15-12) | 101(11-9) | sz(8) | op(7) | 1(6) | M(5) | 0(4) | Vm(3-0)
|
|
ASSERT(!IsIntegerVFPType(dst_type) || !IsIntegerVFPType(src_type));
|
|
|
|
int sz, opc2, op;
|
|
|
|
if (IsIntegerVFPType(dst_type)) {
|
|
opc2 = IsSignedVFPType(dst_type) ? 0x5 : 0x4;
|
|
sz = IsDoubleVFPType(src_type) ? 0x1 : 0x0;
|
|
op = mode;
|
|
} else {
|
|
ASSERT(IsIntegerVFPType(src_type));
|
|
opc2 = 0x0;
|
|
sz = IsDoubleVFPType(dst_type) ? 0x1 : 0x0;
|
|
op = IsSignedVFPType(src_type) ? 0x1 : 0x0;
|
|
}
|
|
|
|
return (cond | 0xE*B24 | B23 | D*B22 | 0x3*B20 | B19 | opc2*B16 |
|
|
Vd*B12 | 0x5*B9 | sz*B8 | op*B7 | B6 | M*B5 | Vm);
|
|
} else {
|
|
// Conversion between IEEE double and single precision.
|
|
// Instruction details available in ARM DDI 0406B, A8.6.298.
|
|
// cond(31-28) | 11101(27-23)| D(22) | 11(21-20) | 0111(19-16) |
|
|
// Vd(15-12) | 101(11-9) | sz(8) | 1(7) | 1(6) | M(5) | 0(4) | Vm(3-0)
|
|
int sz = IsDoubleVFPType(src_type) ? 0x1 : 0x0;
|
|
return (cond | 0xE*B24 | B23 | D*B22 | 0x3*B20 | 0x7*B16 |
|
|
Vd*B12 | 0x5*B9 | sz*B8 | B7 | B6 | M*B5 | Vm);
|
|
}
|
|
}
|
|
|
|
|
|
void Assembler::vcvt_f64_s32(const DwVfpRegister dst,
|
|
const SwVfpRegister src,
|
|
VFPConversionMode mode,
|
|
const Condition cond) {
|
|
ASSERT(CpuFeatures::IsEnabled(VFP3));
|
|
emit(EncodeVCVT(F64, dst.code(), S32, src.code(), mode, cond));
|
|
}
|
|
|
|
|
|
void Assembler::vcvt_f32_s32(const SwVfpRegister dst,
|
|
const SwVfpRegister src,
|
|
VFPConversionMode mode,
|
|
const Condition cond) {
|
|
ASSERT(CpuFeatures::IsEnabled(VFP3));
|
|
emit(EncodeVCVT(F32, dst.code(), S32, src.code(), mode, cond));
|
|
}
|
|
|
|
|
|
void Assembler::vcvt_f64_u32(const DwVfpRegister dst,
|
|
const SwVfpRegister src,
|
|
VFPConversionMode mode,
|
|
const Condition cond) {
|
|
ASSERT(CpuFeatures::IsEnabled(VFP3));
|
|
emit(EncodeVCVT(F64, dst.code(), U32, src.code(), mode, cond));
|
|
}
|
|
|
|
|
|
void Assembler::vcvt_s32_f64(const SwVfpRegister dst,
|
|
const DwVfpRegister src,
|
|
VFPConversionMode mode,
|
|
const Condition cond) {
|
|
ASSERT(CpuFeatures::IsEnabled(VFP3));
|
|
emit(EncodeVCVT(S32, dst.code(), F64, src.code(), mode, cond));
|
|
}
|
|
|
|
|
|
void Assembler::vcvt_u32_f64(const SwVfpRegister dst,
|
|
const DwVfpRegister src,
|
|
VFPConversionMode mode,
|
|
const Condition cond) {
|
|
ASSERT(CpuFeatures::IsEnabled(VFP3));
|
|
emit(EncodeVCVT(U32, dst.code(), F64, src.code(), mode, cond));
|
|
}
|
|
|
|
|
|
void Assembler::vcvt_f64_f32(const DwVfpRegister dst,
|
|
const SwVfpRegister src,
|
|
VFPConversionMode mode,
|
|
const Condition cond) {
|
|
ASSERT(CpuFeatures::IsEnabled(VFP3));
|
|
emit(EncodeVCVT(F64, dst.code(), F32, src.code(), mode, cond));
|
|
}
|
|
|
|
|
|
void Assembler::vcvt_f32_f64(const SwVfpRegister dst,
|
|
const DwVfpRegister src,
|
|
VFPConversionMode mode,
|
|
const Condition cond) {
|
|
ASSERT(CpuFeatures::IsEnabled(VFP3));
|
|
emit(EncodeVCVT(F32, dst.code(), F64, src.code(), mode, cond));
|
|
}
|
|
|
|
|
|
void Assembler::vneg(const DwVfpRegister dst,
|
|
const DwVfpRegister src,
|
|
const Condition cond) {
|
|
emit(cond | 0xE*B24 | 0xB*B20 | B16 | dst.code()*B12 |
|
|
0x5*B9 | B8 | B6 | src.code());
|
|
}
|
|
|
|
|
|
void Assembler::vabs(const DwVfpRegister dst,
|
|
const DwVfpRegister src,
|
|
const Condition cond) {
|
|
emit(cond | 0xE*B24 | 0xB*B20 | dst.code()*B12 |
|
|
0x5*B9 | B8 | 0x3*B6 | src.code());
|
|
}
|
|
|
|
|
|
void Assembler::vadd(const DwVfpRegister dst,
|
|
const DwVfpRegister src1,
|
|
const DwVfpRegister src2,
|
|
const Condition cond) {
|
|
// Dd = vadd(Dn, Dm) double precision floating point addition.
|
|
// Dd = D:Vd; Dm=M:Vm; Dn=N:Vm.
|
|
// Instruction details available in ARM DDI 0406A, A8-536.
|
|
// cond(31-28) | 11100(27-23)| D=?(22) | 11(21-20) | Vn(19-16) |
|
|
// Vd(15-12) | 101(11-9) | sz(8)=1 | N(7)=0 | 0(6) | M=?(5) | 0(4) | Vm(3-0)
|
|
ASSERT(CpuFeatures::IsEnabled(VFP3));
|
|
emit(cond | 0xE*B24 | 0x3*B20 | src1.code()*B16 |
|
|
dst.code()*B12 | 0x5*B9 | B8 | src2.code());
|
|
}
|
|
|
|
|
|
void Assembler::vsub(const DwVfpRegister dst,
|
|
const DwVfpRegister src1,
|
|
const DwVfpRegister src2,
|
|
const Condition cond) {
|
|
// Dd = vsub(Dn, Dm) double precision floating point subtraction.
|
|
// Dd = D:Vd; Dm=M:Vm; Dn=N:Vm.
|
|
// Instruction details available in ARM DDI 0406A, A8-784.
|
|
// cond(31-28) | 11100(27-23)| D=?(22) | 11(21-20) | Vn(19-16) |
|
|
// Vd(15-12) | 101(11-9) | sz(8)=1 | N(7)=0 | 1(6) | M=?(5) | 0(4) | Vm(3-0)
|
|
ASSERT(CpuFeatures::IsEnabled(VFP3));
|
|
emit(cond | 0xE*B24 | 0x3*B20 | src1.code()*B16 |
|
|
dst.code()*B12 | 0x5*B9 | B8 | B6 | src2.code());
|
|
}
|
|
|
|
|
|
void Assembler::vmul(const DwVfpRegister dst,
|
|
const DwVfpRegister src1,
|
|
const DwVfpRegister src2,
|
|
const Condition cond) {
|
|
// Dd = vmul(Dn, Dm) double precision floating point multiplication.
|
|
// Dd = D:Vd; Dm=M:Vm; Dn=N:Vm.
|
|
// Instruction details available in ARM DDI 0406A, A8-784.
|
|
// cond(31-28) | 11100(27-23)| D=?(22) | 10(21-20) | Vn(19-16) |
|
|
// Vd(15-12) | 101(11-9) | sz(8)=1 | N(7)=0 | 0(6) | M=?(5) | 0(4) | Vm(3-0)
|
|
ASSERT(CpuFeatures::IsEnabled(VFP3));
|
|
emit(cond | 0xE*B24 | 0x2*B20 | src1.code()*B16 |
|
|
dst.code()*B12 | 0x5*B9 | B8 | src2.code());
|
|
}
|
|
|
|
|
|
void Assembler::vdiv(const DwVfpRegister dst,
|
|
const DwVfpRegister src1,
|
|
const DwVfpRegister src2,
|
|
const Condition cond) {
|
|
// Dd = vdiv(Dn, Dm) double precision floating point division.
|
|
// Dd = D:Vd; Dm=M:Vm; Dn=N:Vm.
|
|
// Instruction details available in ARM DDI 0406A, A8-584.
|
|
// cond(31-28) | 11101(27-23)| D=?(22) | 00(21-20) | Vn(19-16) |
|
|
// Vd(15-12) | 101(11-9) | sz(8)=1 | N(7)=? | 0(6) | M=?(5) | 0(4) | Vm(3-0)
|
|
ASSERT(CpuFeatures::IsEnabled(VFP3));
|
|
emit(cond | 0xE*B24 | B23 | src1.code()*B16 |
|
|
dst.code()*B12 | 0x5*B9 | B8 | src2.code());
|
|
}
|
|
|
|
|
|
void Assembler::vcmp(const DwVfpRegister src1,
|
|
const DwVfpRegister src2,
|
|
const Condition cond) {
|
|
// vcmp(Dd, Dm) double precision floating point comparison.
|
|
// Instruction details available in ARM DDI 0406A, A8-570.
|
|
// cond(31-28) | 11101 (27-23)| D=?(22) | 11 (21-20) | 0100 (19-16) |
|
|
// Vd(15-12) | 101(11-9) | sz(8)=1 | E(7)=0 | 1(6) | M(5)=? | 0(4) | Vm(3-0)
|
|
ASSERT(CpuFeatures::IsEnabled(VFP3));
|
|
emit(cond | 0xE*B24 |B23 | 0x3*B20 | B18 |
|
|
src1.code()*B12 | 0x5*B9 | B8 | B6 | src2.code());
|
|
}
|
|
|
|
|
|
void Assembler::vcmp(const DwVfpRegister src1,
|
|
const double src2,
|
|
const Condition cond) {
|
|
// vcmp(Dd, Dm) double precision floating point comparison.
|
|
// Instruction details available in ARM DDI 0406A, A8-570.
|
|
// cond(31-28) | 11101 (27-23)| D=?(22) | 11 (21-20) | 0101 (19-16) |
|
|
// Vd(15-12) | 101(11-9) | sz(8)=1 | E(7)=0 | 1(6) | M(5)=? | 0(4) | 0000(3-0)
|
|
ASSERT(CpuFeatures::IsEnabled(VFP3));
|
|
ASSERT(src2 == 0.0);
|
|
emit(cond | 0xE*B24 |B23 | 0x3*B20 | B18 | B16 |
|
|
src1.code()*B12 | 0x5*B9 | B8 | B6);
|
|
}
|
|
|
|
|
|
void Assembler::vmsr(Register dst, Condition cond) {
|
|
// Instruction details available in ARM DDI 0406A, A8-652.
|
|
// cond(31-28) | 1110 (27-24) | 1110(23-20)| 0001 (19-16) |
|
|
// Rt(15-12) | 1010 (11-8) | 0(7) | 00 (6-5) | 1(4) | 0000(3-0)
|
|
ASSERT(CpuFeatures::IsEnabled(VFP3));
|
|
emit(cond | 0xE*B24 | 0xE*B20 | B16 |
|
|
dst.code()*B12 | 0xA*B8 | B4);
|
|
}
|
|
|
|
|
|
void Assembler::vmrs(Register dst, Condition cond) {
|
|
// Instruction details available in ARM DDI 0406A, A8-652.
|
|
// cond(31-28) | 1110 (27-24) | 1111(23-20)| 0001 (19-16) |
|
|
// Rt(15-12) | 1010 (11-8) | 0(7) | 00 (6-5) | 1(4) | 0000(3-0)
|
|
ASSERT(CpuFeatures::IsEnabled(VFP3));
|
|
emit(cond | 0xE*B24 | 0xF*B20 | B16 |
|
|
dst.code()*B12 | 0xA*B8 | B4);
|
|
}
|
|
|
|
|
|
void Assembler::vsqrt(const DwVfpRegister dst,
|
|
const DwVfpRegister src,
|
|
const Condition cond) {
|
|
// cond(31-28) | 11101 (27-23)| D=?(22) | 11 (21-20) | 0001 (19-16) |
|
|
// Vd(15-12) | 101(11-9) | sz(8)=1 | 11 (7-6) | M(5)=? | 0(4) | Vm(3-0)
|
|
ASSERT(CpuFeatures::IsEnabled(VFP3));
|
|
emit(cond | 0xE*B24 | B23 | 0x3*B20 | B16 |
|
|
dst.code()*B12 | 0x5*B9 | B8 | 3*B6 | src.code());
|
|
}
|
|
|
|
|
|
// Pseudo instructions.
|
|
void Assembler::nop(int type) {
|
|
// This is mov rx, rx.
|
|
ASSERT(0 <= type && type <= 14); // mov pc, pc is not a nop.
|
|
emit(al | 13*B21 | type*B12 | type);
|
|
}
|
|
|
|
|
|
bool Assembler::IsNop(Instr instr, int type) {
|
|
// Check for mov rx, rx where x = type.
|
|
ASSERT(0 <= type && type <= 14); // mov pc, pc is not a nop.
|
|
return instr == (al | 13*B21 | type*B12 | type);
|
|
}
|
|
|
|
|
|
bool Assembler::ImmediateFitsAddrMode1Instruction(int32_t imm32) {
|
|
uint32_t dummy1;
|
|
uint32_t dummy2;
|
|
return fits_shifter(imm32, &dummy1, &dummy2, NULL);
|
|
}
|
|
|
|
|
|
// Debugging.
|
|
void Assembler::RecordJSReturn() {
|
|
positions_recorder()->WriteRecordedPositions();
|
|
CheckBuffer();
|
|
RecordRelocInfo(RelocInfo::JS_RETURN);
|
|
}
|
|
|
|
|
|
void Assembler::RecordDebugBreakSlot() {
|
|
positions_recorder()->WriteRecordedPositions();
|
|
CheckBuffer();
|
|
RecordRelocInfo(RelocInfo::DEBUG_BREAK_SLOT);
|
|
}
|
|
|
|
|
|
void Assembler::RecordComment(const char* msg) {
|
|
if (FLAG_code_comments) {
|
|
CheckBuffer();
|
|
RecordRelocInfo(RelocInfo::COMMENT, reinterpret_cast<intptr_t>(msg));
|
|
}
|
|
}
|
|
|
|
|
|
void Assembler::GrowBuffer() {
|
|
if (!own_buffer_) FATAL("external code buffer is too small");
|
|
|
|
// Compute new buffer size.
|
|
CodeDesc desc; // the new buffer
|
|
if (buffer_size_ < 4*KB) {
|
|
desc.buffer_size = 4*KB;
|
|
} else if (buffer_size_ < 1*MB) {
|
|
desc.buffer_size = 2*buffer_size_;
|
|
} else {
|
|
desc.buffer_size = buffer_size_ + 1*MB;
|
|
}
|
|
CHECK_GT(desc.buffer_size, 0); // no overflow
|
|
|
|
// Set up new buffer.
|
|
desc.buffer = NewArray<byte>(desc.buffer_size);
|
|
|
|
desc.instr_size = pc_offset();
|
|
desc.reloc_size = (buffer_ + buffer_size_) - reloc_info_writer.pos();
|
|
|
|
// Copy the data.
|
|
int pc_delta = desc.buffer - buffer_;
|
|
int rc_delta = (desc.buffer + desc.buffer_size) - (buffer_ + buffer_size_);
|
|
memmove(desc.buffer, buffer_, desc.instr_size);
|
|
memmove(reloc_info_writer.pos() + rc_delta,
|
|
reloc_info_writer.pos(), desc.reloc_size);
|
|
|
|
// Switch buffers.
|
|
DeleteArray(buffer_);
|
|
buffer_ = desc.buffer;
|
|
buffer_size_ = desc.buffer_size;
|
|
pc_ += pc_delta;
|
|
reloc_info_writer.Reposition(reloc_info_writer.pos() + rc_delta,
|
|
reloc_info_writer.last_pc() + pc_delta);
|
|
|
|
// None of our relocation types are pc relative pointing outside the code
|
|
// buffer nor pc absolute pointing inside the code buffer, so there is no need
|
|
// to relocate any emitted relocation entries.
|
|
|
|
// Relocate pending relocation entries.
|
|
for (int i = 0; i < num_pending_reloc_info_; i++) {
|
|
RelocInfo& rinfo = pending_reloc_info_[i];
|
|
ASSERT(rinfo.rmode() != RelocInfo::COMMENT &&
|
|
rinfo.rmode() != RelocInfo::POSITION);
|
|
if (rinfo.rmode() != RelocInfo::JS_RETURN) {
|
|
rinfo.set_pc(rinfo.pc() + pc_delta);
|
|
}
|
|
}
|
|
}
|
|
|
|
|
|
void Assembler::db(uint8_t data) {
|
|
// No relocation info should be pending while using db. db is used
|
|
// to write pure data with no pointers and the constant pool should
|
|
// be emitted before using db.
|
|
ASSERT(num_pending_reloc_info_ == 0);
|
|
CheckBuffer();
|
|
*reinterpret_cast<uint8_t*>(pc_) = data;
|
|
pc_ += sizeof(uint8_t);
|
|
}
|
|
|
|
|
|
void Assembler::dd(uint32_t data) {
|
|
// No relocation info should be pending while using dd. dd is used
|
|
// to write pure data with no pointers and the constant pool should
|
|
// be emitted before using dd.
|
|
ASSERT(num_pending_reloc_info_ == 0);
|
|
CheckBuffer();
|
|
*reinterpret_cast<uint32_t*>(pc_) = data;
|
|
pc_ += sizeof(uint32_t);
|
|
}
|
|
|
|
|
|
void Assembler::RecordRelocInfo(RelocInfo::Mode rmode, intptr_t data) {
|
|
// We do not try to reuse pool constants.
|
|
RelocInfo rinfo(pc_, rmode, data, NULL);
|
|
if (rmode >= RelocInfo::JS_RETURN && rmode <= RelocInfo::DEBUG_BREAK_SLOT) {
|
|
// Adjust code for new modes.
|
|
ASSERT(RelocInfo::IsDebugBreakSlot(rmode)
|
|
|| RelocInfo::IsJSReturn(rmode)
|
|
|| RelocInfo::IsComment(rmode)
|
|
|| RelocInfo::IsPosition(rmode));
|
|
// These modes do not need an entry in the constant pool.
|
|
} else {
|
|
ASSERT(num_pending_reloc_info_ < kMaxNumPendingRelocInfo);
|
|
if (num_pending_reloc_info_ == 0) {
|
|
first_const_pool_use_ = pc_offset();
|
|
}
|
|
pending_reloc_info_[num_pending_reloc_info_++] = rinfo;
|
|
// Make sure the constant pool is not emitted in place of the next
|
|
// instruction for which we just recorded relocation info.
|
|
BlockConstPoolFor(1);
|
|
}
|
|
if (rinfo.rmode() != RelocInfo::NONE) {
|
|
// Don't record external references unless the heap will be serialized.
|
|
if (rmode == RelocInfo::EXTERNAL_REFERENCE) {
|
|
#ifdef DEBUG
|
|
if (!Serializer::enabled()) {
|
|
Serializer::TooLateToEnableNow();
|
|
}
|
|
#endif
|
|
if (!Serializer::enabled() && !emit_debug_code()) {
|
|
return;
|
|
}
|
|
}
|
|
ASSERT(buffer_space() >= kMaxRelocSize); // too late to grow buffer here
|
|
if (rmode == RelocInfo::CODE_TARGET_WITH_ID) {
|
|
RelocInfo reloc_info_with_ast_id(pc_, rmode, RecordedAstId(), NULL);
|
|
ClearRecordedAstId();
|
|
reloc_info_writer.Write(&reloc_info_with_ast_id);
|
|
} else {
|
|
reloc_info_writer.Write(&rinfo);
|
|
}
|
|
}
|
|
}
|
|
|
|
|
|
void Assembler::BlockConstPoolFor(int instructions) {
|
|
int pc_limit = pc_offset() + instructions * kInstrSize;
|
|
if (no_const_pool_before_ < pc_limit) {
|
|
// If there are some pending entries, the constant pool cannot be blocked
|
|
// further than first_const_pool_use_ + kMaxDistToPool
|
|
ASSERT((num_pending_reloc_info_ == 0) ||
|
|
(pc_limit < (first_const_pool_use_ + kMaxDistToPool)));
|
|
no_const_pool_before_ = pc_limit;
|
|
}
|
|
|
|
if (next_buffer_check_ < no_const_pool_before_) {
|
|
next_buffer_check_ = no_const_pool_before_;
|
|
}
|
|
}
|
|
|
|
|
|
void Assembler::CheckConstPool(bool force_emit, bool require_jump) {
|
|
// Some short sequence of instruction mustn't be broken up by constant pool
|
|
// emission, such sequences are protected by calls to BlockConstPoolFor and
|
|
// BlockConstPoolScope.
|
|
if (is_const_pool_blocked()) {
|
|
// Something is wrong if emission is forced and blocked at the same time.
|
|
ASSERT(!force_emit);
|
|
return;
|
|
}
|
|
|
|
// There is nothing to do if there are no pending constant pool entries.
|
|
if (num_pending_reloc_info_ == 0) {
|
|
// Calculate the offset of the next check.
|
|
next_buffer_check_ = pc_offset() + kCheckPoolInterval;
|
|
return;
|
|
}
|
|
|
|
// We emit a constant pool when:
|
|
// * requested to do so by parameter force_emit (e.g. after each function).
|
|
// * the distance to the first instruction accessing the constant pool is
|
|
// kAvgDistToPool or more.
|
|
// * no jump is required and the distance to the first instruction accessing
|
|
// the constant pool is at least kMaxDistToPool / 2.
|
|
ASSERT(first_const_pool_use_ >= 0);
|
|
int dist = pc_offset() - first_const_pool_use_;
|
|
if (!force_emit && dist < kAvgDistToPool &&
|
|
(require_jump || (dist < (kMaxDistToPool / 2)))) {
|
|
return;
|
|
}
|
|
|
|
// Check that the code buffer is large enough before emitting the constant
|
|
// pool (include the jump over the pool and the constant pool marker and
|
|
// the gap to the relocation information).
|
|
int jump_instr = require_jump ? kInstrSize : 0;
|
|
int needed_space = jump_instr + kInstrSize +
|
|
num_pending_reloc_info_ * kInstrSize + kGap;
|
|
while (buffer_space() <= needed_space) GrowBuffer();
|
|
|
|
{
|
|
// Block recursive calls to CheckConstPool.
|
|
BlockConstPoolScope block_const_pool(this);
|
|
|
|
// Emit jump over constant pool if necessary.
|
|
Label after_pool;
|
|
if (require_jump) {
|
|
b(&after_pool);
|
|
}
|
|
|
|
RecordComment("[ Constant Pool");
|
|
|
|
// Put down constant pool marker "Undefined instruction" as specified by
|
|
// A5.6 (ARMv7) Instruction set encoding.
|
|
emit(kConstantPoolMarker | num_pending_reloc_info_);
|
|
|
|
// Emit constant pool entries.
|
|
for (int i = 0; i < num_pending_reloc_info_; i++) {
|
|
RelocInfo& rinfo = pending_reloc_info_[i];
|
|
ASSERT(rinfo.rmode() != RelocInfo::COMMENT &&
|
|
rinfo.rmode() != RelocInfo::POSITION &&
|
|
rinfo.rmode() != RelocInfo::STATEMENT_POSITION);
|
|
|
|
Instr instr = instr_at(rinfo.pc());
|
|
// Instruction to patch must be 'ldr rd, [pc, #offset]' with offset == 0.
|
|
ASSERT(IsLdrPcImmediateOffset(instr) &&
|
|
GetLdrRegisterImmediateOffset(instr) == 0);
|
|
|
|
int delta = pc_ - rinfo.pc() - kPcLoadDelta;
|
|
// 0 is the smallest delta:
|
|
// ldr rd, [pc, #0]
|
|
// constant pool marker
|
|
// data
|
|
ASSERT(is_uint12(delta));
|
|
|
|
instr_at_put(rinfo.pc(), SetLdrRegisterImmediateOffset(instr, delta));
|
|
emit(rinfo.data());
|
|
}
|
|
|
|
num_pending_reloc_info_ = 0;
|
|
first_const_pool_use_ = -1;
|
|
|
|
RecordComment("]");
|
|
|
|
if (after_pool.is_linked()) {
|
|
bind(&after_pool);
|
|
}
|
|
}
|
|
|
|
// Since a constant pool was just emitted, move the check offset forward by
|
|
// the standard interval.
|
|
next_buffer_check_ = pc_offset() + kCheckPoolInterval;
|
|
}
|
|
|
|
|
|
} } // namespace v8::internal
|
|
|
|
#endif // V8_TARGET_ARCH_ARM
|
|
|