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127 lines
4.5 KiB
127 lines
4.5 KiB
// Copyright 2006-2009 the V8 project authors. All rights reserved.
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met:
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//
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// * Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// * Redistributions in binary form must reproduce the above
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// copyright notice, this list of conditions and the following
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// disclaimer in the documentation and/or other materials provided
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// with the distribution.
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// * Neither the name of Google Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// CPU specific code for arm independent of OS goes here.
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#if defined(__arm__)
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#include <sys/syscall.h> // for cache flushing.
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#endif
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#include "v8.h"
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#include "cpu.h"
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namespace v8 {
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namespace internal {
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void CPU::Setup() {
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// Nothing to do.
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}
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void CPU::FlushICache(void* start, size_t size) {
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#if !defined (__arm__)
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// Not generating ARM instructions for C-code. This means that we are
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// building an ARM emulator based target. No I$ flushes are necessary.
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// None of this code ends up in the snapshot so there are no issues
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// around whether or not to generate the code when building snapshots.
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#else
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// Ideally, we would call
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// syscall(__ARM_NR_cacheflush, start,
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// reinterpret_cast<intptr_t>(start) + size, 0);
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// however, syscall(int, ...) is not supported on all platforms, especially
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// not when using EABI, so we call the __ARM_NR_cacheflush syscall directly.
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register uint32_t beg asm("a1") = reinterpret_cast<uint32_t>(start);
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register uint32_t end asm("a2") =
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reinterpret_cast<uint32_t>(start) + size;
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register uint32_t flg asm("a3") = 0;
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#ifdef __ARM_EABI__
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register uint32_t scno asm("r7") = __ARM_NR_cacheflush;
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#if defined (__arm__) && !defined(__thumb__)
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// __arm__ may be defined in thumb mode.
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asm volatile(
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"swi 0x0"
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: "=r" (beg)
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: "0" (beg), "r" (end), "r" (flg), "r" (scno));
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#else
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asm volatile(
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"@ Enter ARM Mode \n\t"
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"adr r3, 1f \n\t"
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"bx r3 \n\t"
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".ALIGN 4 \n\t"
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".ARM \n"
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"1: swi 0x0 \n\t"
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"@ Enter THUMB Mode\n\t"
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"adr r3, 2f+1 \n\t"
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"bx r3 \n\t"
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".THUMB \n"
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"2: \n\t"
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: "=r" (beg)
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: "0" (beg), "r" (end), "r" (flg), "r" (scno)
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: "r3");
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#endif
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#else
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#if defined (__arm__) && !defined(__thumb__)
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// __arm__ may be defined in thumb mode.
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asm volatile(
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"swi %1"
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: "=r" (beg)
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: "i" (__ARM_NR_cacheflush), "0" (beg), "r" (end), "r" (flg));
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#else
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// Do not use the value of __ARM_NR_cacheflush in the inline assembly
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// below, because the thumb mode value would be used, which would be
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// wrong, since we switch to ARM mode before executing the swi instruction
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asm volatile(
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"@ Enter ARM Mode \n\t"
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"adr r3, 1f \n\t"
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"bx r3 \n\t"
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".ALIGN 4 \n\t"
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".ARM \n"
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"1: swi 0x9f0002 \n"
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"@ Enter THUMB Mode\n\t"
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"adr r3, 2f+1 \n\t"
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"bx r3 \n\t"
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".THUMB \n"
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"2: \n\t"
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: "=r" (beg)
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: "0" (beg), "r" (end), "r" (flg)
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: "r3");
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#endif
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#endif
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#endif
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}
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void CPU::DebugBreak() {
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#if !defined (__arm__)
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UNIMPLEMENTED(); // when building ARM emulator target
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#else
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asm volatile("bkpt 0");
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#endif
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}
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} } // namespace v8::internal
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