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162 lines
5.5 KiB
162 lines
5.5 KiB
4 years ago
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/*
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* Copyright (c) 2018 - 2019, Nordic Semiconductor ASA
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef NRFX_IRQS_NRF9160_H__
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#define NRFX_IRQS_NRF9160_H__
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#ifdef __cplusplus
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extern "C" {
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#endif
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// SPU_IRQn
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// CLOCK_POWER_IRQn
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#define nrfx_power_clock_irq_handler CLOCK_POWER_IRQHandler
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// UARTE0_SPIM0_SPIS0_TWIM0_TWIS0_IRQn
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#if NRFX_CHECK(NRFX_PRS_ENABLED) && NRFX_CHECK(NRFX_PRS_BOX_0_ENABLED)
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#define nrfx_prs_box_0_irq_handler UARTE0_SPIM0_SPIS0_TWIM0_TWIS0_IRQHandler
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#else
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#define nrfx_spim_0_irq_handler UARTE0_SPIM0_SPIS0_TWIM0_TWIS0_IRQHandler
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#define nrfx_spis_0_irq_handler UARTE0_SPIM0_SPIS0_TWIM0_TWIS0_IRQHandler
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#define nrfx_twim_0_irq_handler UARTE0_SPIM0_SPIS0_TWIM0_TWIS0_IRQHandler
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#define nrfx_twis_0_irq_handler UARTE0_SPIM0_SPIS0_TWIM0_TWIS0_IRQHandler
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#define nrfx_uarte_0_irq_handler UARTE0_SPIM0_SPIS0_TWIM0_TWIS0_IRQHandler
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#endif
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// UARTE1_SPIM1_SPIS1_TWIM1_TWIS1_IRQn
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#if NRFX_CHECK(NRFX_PRS_ENABLED) && NRFX_CHECK(NRFX_PRS_BOX_1_ENABLED)
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#define nrfx_prs_box_1_irq_handler UARTE1_SPIM1_SPIS1_TWIM1_TWIS1_IRQHandler
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#else
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#define nrfx_spim_1_irq_handler UARTE1_SPIM1_SPIS1_TWIM1_TWIS1_IRQHandler
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#define nrfx_spis_1_irq_handler UARTE1_SPIM1_SPIS1_TWIM1_TWIS1_IRQHandler
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#define nrfx_twim_1_irq_handler UARTE1_SPIM1_SPIS1_TWIM1_TWIS1_IRQHandler
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#define nrfx_twis_1_irq_handler UARTE1_SPIM1_SPIS1_TWIM1_TWIS1_IRQHandler
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#define nrfx_uarte_1_irq_handler UARTE1_SPIM1_SPIS1_TWIM1_TWIS1_IRQHandler
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#endif
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// UARTE2_SPIM2_SPIS2_TWIM2_TWIS2_IRQn
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#if NRFX_CHECK(NRFX_PRS_ENABLED) && NRFX_CHECK(NRFX_PRS_BOX_2_ENABLED)
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#define nrfx_prs_box_2_irq_handler UARTE2_SPIM2_SPIS2_TWIM2_TWIS2_IRQHandler
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#else
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#define nrfx_spim_2_irq_handler UARTE2_SPIM2_SPIS2_TWIM2_TWIS2_IRQHandler
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#define nrfx_spis_2_irq_handler UARTE2_SPIM2_SPIS2_TWIM2_TWIS2_IRQHandler
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#define nrfx_twim_2_irq_handler UARTE2_SPIM2_SPIS2_TWIM2_TWIS2_IRQHandler
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#define nrfx_twis_2_irq_handler UARTE2_SPIM2_SPIS2_TWIM2_TWIS2_IRQHandler
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#define nrfx_uarte_2_irq_handler UARTE2_SPIM2_SPIS2_TWIM2_TWIS2_IRQHandler
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#endif
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// UARTE3_SPIM3_SPIS3_TWIM3_TWIS3_IRQn
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#if NRFX_CHECK(NRFX_PRS_ENABLED) && NRFX_CHECK(NRFX_PRS_BOX_3_ENABLED)
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#define nrfx_prs_box_3_irq_handler UARTE3_SPIM3_SPIS3_TWIM3_TWIS3_IRQHandler
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#else
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#define nrfx_spim_3_irq_handler UARTE3_SPIM3_SPIS3_TWIM3_TWIS3_IRQHandler
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#define nrfx_spis_3_irq_handler UARTE3_SPIM3_SPIS3_TWIM3_TWIS3_IRQHandler
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#define nrfx_twim_3_irq_handler UARTE3_SPIM3_SPIS3_TWIM3_TWIS3_IRQHandler
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#define nrfx_twis_3_irq_handler UARTE3_SPIM3_SPIS3_TWIM3_TWIS3_IRQHandler
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#define nrfx_uarte_3_irq_handler UARTE3_SPIM3_SPIS3_TWIM3_TWIS3_IRQHandler
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#endif
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// GPIOTE0_IRQn
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#define nrfx_gpiote_irq_handler GPIOTE_IRQHandler
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// SAADC_IRQn
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#define nrfx_saadc_irq_handler SAADC_IRQHandler
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// TIMER0_IRQn
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#define nrfx_timer_0_irq_handler TIMER0_IRQHandler
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// TIMER1_IRQn
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#define nrfx_timer_1_irq_handler TIMER1_IRQHandler
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// TIMER2_IRQn
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#define nrfx_timer_2_irq_handler TIMER2_IRQHandler
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// RTC0_IRQn
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#define nrfx_rtc_0_irq_handler RTC0_IRQHandler
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// RTC1_IRQn
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#define nrfx_rtc_1_irq_handler RTC1_IRQHandler
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// WDT_IRQn
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#define nrfx_wdt_irq_handler WDT_IRQHandler
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// EGU0_IRQn
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#define nrfx_swi_0_irq_handler EGU0_IRQHandler
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// EGU1_IRQn
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#define nrfx_swi_1_irq_handler EGU1_IRQHandler
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// EGU2_IRQn
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#define nrfx_swi_2_irq_handler EGU2_IRQHandler
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// EGU3_IRQn
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#define nrfx_swi_3_irq_handler EGU3_IRQHandler
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// EGU4_IRQn
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#define nrfx_swi_4_irq_handler EGU4_IRQHandler
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// EGU5_IRQn
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#define nrfx_swi_5_irq_handler EGU5_IRQHandler
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// PWM0_IRQn
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#define nrfx_pwm_0_irq_handler PWM0_IRQHandler
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// PWM1_IRQn
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#define nrfx_pwm_1_irq_handler PWM1_IRQHandler
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// PWM2_IRQn
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#define nrfx_pwm_2_irq_handler PWM2_IRQHandler
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// PWM3_IRQn
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#define nrfx_pwm_3_irq_handler PWM3_IRQHandler
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// PDM_IRQn
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#define nrfx_pdm_irq_handler PDM_IRQHandler
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// I2S_IRQn
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#define nrfx_i2s_irq_handler I2S_IRQHandler
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// FPU_IRQn
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// GPIOTE1_IRQn
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// KMU_IRQn
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// CRYPTOCELL_IRQn
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#ifdef __cplusplus
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}
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#endif
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#endif // NRFX_IRQS_NRF9160_H__
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