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265 lines
9.2 KiB
265 lines
9.2 KiB
4 years ago
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// SPDX-FileCopyrightText: 2020 Foundation Devices, Inc. <hello@foundationdevices.com>
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// SPDX-License-Identifier: GPL-3.0-or-later
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//
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// SPDX-FileCopyrightText: 2018 Coinkite, Inc. <coldcardwallet.com>
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// SPDX-License-Identifier: GPL-3.0-only
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//
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#include <errno.h>
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#include <string.h>
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#include "../stm32h7xx_hal_conf.h"
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#include "stm32h7xx_ll_cortex.h"
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#include "pprng.h"
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#include "secrets.h"
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#include "se.h"
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#include "se-atecc608a.h"
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#include "utils.h"
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#include "flash.h"
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#include "verify.h"
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#include "update.h"
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void SysTick_Handler(void)
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{
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HAL_IncTick();
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}
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static void SystemClock_Config(void)
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{
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HAL_StatusTypeDef rc;
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RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
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RCC_OscInitTypeDef RCC_OscInitStruct = {0};
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RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
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/*!< Supply configuration update enable */
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rc = HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY);
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if (rc != HAL_OK)
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return;
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__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
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while(!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {}
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/* Enable HSE Oscillator and activate PLL with HSE as source */
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RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI48;
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RCC_OscInitStruct.HSEState = RCC_HSE_ON;
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RCC_OscInitStruct.HSIState = RCC_HSI_OFF;
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RCC_OscInitStruct.CSIState = RCC_CSI_OFF;
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RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
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RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
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RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
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RCC_OscInitStruct.PLL.PLLM = 1;
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RCC_OscInitStruct.PLL.PLLN = 120;
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RCC_OscInitStruct.PLL.PLLP = 2;
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RCC_OscInitStruct.PLL.PLLQ = 120;
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RCC_OscInitStruct.PLL.PLLR = 2;
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RCC_OscInitStruct.PLL.PLLFRACN = 0;
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RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE;
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RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_1;
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rc = HAL_RCC_OscConfig(&RCC_OscInitStruct);
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if (rc != HAL_OK)
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{
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while(1) { ; }
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}
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PeriphClkInitStruct.PeriphClockSelection =
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RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_RNG;
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PeriphClkInitStruct.PLL2.PLL2M = 1;
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PeriphClkInitStruct.PLL2.PLL2N = 18;
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PeriphClkInitStruct.PLL2.PLL2P = 1;
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PeriphClkInitStruct.PLL2.PLL2Q = 2;
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PeriphClkInitStruct.PLL2.PLL2R = 2;
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PeriphClkInitStruct.PLL2.PLL2RGE = RCC_PLL2VCIRANGE_3;
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PeriphClkInitStruct.PLL2.PLL2VCOSEL = RCC_PLL2VCOMEDIUM;
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PeriphClkInitStruct.PLL2.PLL2FRACN = 6144;
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PeriphClkInitStruct.Usart234578ClockSelection = RCC_USART234578CLKSOURCE_D2PCLK1;
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PeriphClkInitStruct.RngClockSelection = RCC_RNGCLKSOURCE_HSI48;
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PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSI;
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rc = HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
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if (rc != HAL_OK)
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{
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while(1) { ; }
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}
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RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_D1PCLK1 | RCC_CLOCKTYPE_PCLK1 | \
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RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_D3PCLK1);
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RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
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RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1;
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RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2;
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RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2;
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RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2;
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RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2;
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RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2;
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rc = HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4);
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if (rc != HAL_OK)
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{
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while(1) { ; }
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}
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__HAL_RCC_CSI_ENABLE() ;
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__HAL_RCC_SYSCFG_CLK_ENABLE() ;
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__HAL_RCC_GPIOA_CLK_ENABLE();
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__HAL_RCC_GPIOB_CLK_ENABLE();
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__HAL_RCC_GPIOC_CLK_ENABLE();
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__HAL_RCC_GPIOD_CLK_ENABLE();
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__HAL_RCC_GPIOE_CLK_ENABLE();
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__HAL_RCC_D2SRAM1_CLK_ENABLE();
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__HAL_RCC_D2SRAM2_CLK_ENABLE();
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__HAL_RCC_D2SRAM3_CLK_ENABLE();
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}
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void MPU_Config(void)
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{
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MPU_Region_InitTypeDef MPU_InitStruct;
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/* Disable MPU */
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HAL_MPU_Disable();
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/* Configure AXI SRAM region as non-executable */
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memset(&MPU_InitStruct, 0, sizeof(MPU_InitStruct));
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MPU_InitStruct.Enable = MPU_REGION_ENABLE;
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MPU_InitStruct.BaseAddress = 0x24000000;
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MPU_InitStruct.Size = MPU_REGION_SIZE_512KB;
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MPU_InitStruct.AccessPermission = MPU_REGION_FULL_ACCESS;
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MPU_InitStruct.IsBufferable = MPU_ACCESS_NOT_BUFFERABLE;
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MPU_InitStruct.IsCacheable = MPU_ACCESS_CACHEABLE;
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MPU_InitStruct.IsShareable = MPU_ACCESS_SHAREABLE;
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MPU_InitStruct.Number = MPU_REGION_NUMBER0;
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MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0;
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MPU_InitStruct.SubRegionDisable = 0x00;
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MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_DISABLE;
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HAL_MPU_ConfigRegion(&MPU_InitStruct);
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/* Configure SRAM1 region as non-executable */
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memset(&MPU_InitStruct, 0, sizeof(MPU_InitStruct));
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MPU_InitStruct.Enable = MPU_REGION_ENABLE;
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MPU_InitStruct.BaseAddress = 0x30000000;
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MPU_InitStruct.Size = MPU_REGION_SIZE_128KB;
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MPU_InitStruct.AccessPermission = MPU_REGION_FULL_ACCESS;
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MPU_InitStruct.IsBufferable = MPU_ACCESS_NOT_BUFFERABLE;
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MPU_InitStruct.IsCacheable = MPU_ACCESS_CACHEABLE;
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MPU_InitStruct.IsShareable = MPU_ACCESS_SHAREABLE;
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MPU_InitStruct.Number = MPU_REGION_NUMBER1;
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MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0;
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MPU_InitStruct.SubRegionDisable = 0x00;
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MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_DISABLE;
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HAL_MPU_ConfigRegion(&MPU_InitStruct);
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/* Configure SRAM2 region as non-executable */
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memset(&MPU_InitStruct, 0, sizeof(MPU_InitStruct));
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MPU_InitStruct.Enable = MPU_REGION_ENABLE;
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MPU_InitStruct.BaseAddress = 0x30020000;
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MPU_InitStruct.Size = MPU_REGION_SIZE_128KB;
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MPU_InitStruct.AccessPermission = MPU_REGION_FULL_ACCESS;
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MPU_InitStruct.IsBufferable = MPU_ACCESS_NOT_BUFFERABLE;
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MPU_InitStruct.IsCacheable = MPU_ACCESS_CACHEABLE;
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MPU_InitStruct.IsShareable = MPU_ACCESS_SHAREABLE;
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MPU_InitStruct.Number = MPU_REGION_NUMBER2;
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MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0;
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MPU_InitStruct.SubRegionDisable = 0x00;
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MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_DISABLE;
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HAL_MPU_ConfigRegion(&MPU_InitStruct);
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/* Configure SRAM3 region as non-executable */
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memset(&MPU_InitStruct, 0, sizeof(MPU_InitStruct));
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MPU_InitStruct.Enable = MPU_REGION_ENABLE;
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MPU_InitStruct.BaseAddress = 0x30040000;
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MPU_InitStruct.Size = MPU_REGION_SIZE_32KB;
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MPU_InitStruct.AccessPermission = MPU_REGION_FULL_ACCESS;
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MPU_InitStruct.IsBufferable = MPU_ACCESS_NOT_BUFFERABLE;
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MPU_InitStruct.IsCacheable = MPU_ACCESS_CACHEABLE;
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MPU_InitStruct.IsShareable = MPU_ACCESS_SHAREABLE;
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MPU_InitStruct.Number = MPU_REGION_NUMBER3;
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MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0;
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MPU_InitStruct.SubRegionDisable = 0x00;
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MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_DISABLE;
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HAL_MPU_ConfigRegion(&MPU_InitStruct);
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#if 0 /* FIXME...enabling this causes an IACCVIOL! */
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/* Configure SRAM4 region as non-executable */
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memset(&MPU_InitStruct, 0, sizeof(MPU_InitStruct));
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MPU_InitStruct.Enable = MPU_REGION_ENABLE;
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MPU_InitStruct.BaseAddress = 0x38000000;
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MPU_InitStruct.Size = MPU_REGION_SIZE_64KB;
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MPU_InitStruct.AccessPermission = MPU_REGION_FULL_ACCESS;
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MPU_InitStruct.IsBufferable = MPU_ACCESS_NOT_BUFFERABLE;
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MPU_InitStruct.IsCacheable = MPU_ACCESS_CACHEABLE;
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MPU_InitStruct.IsShareable = MPU_ACCESS_SHAREABLE;
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MPU_InitStruct.Number = MPU_REGION_NUMBER4;
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MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0;
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MPU_InitStruct.SubRegionDisable = 0x00;
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MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_DISABLE;
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HAL_MPU_ConfigRegion(&MPU_InitStruct);
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#endif
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/* Configure ITCM region as non-executable */
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memset(&MPU_InitStruct, 0, sizeof(MPU_InitStruct));
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MPU_InitStruct.Enable = MPU_REGION_ENABLE;
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MPU_InitStruct.BaseAddress = 0x00000000;
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MPU_InitStruct.Size = MPU_REGION_SIZE_64KB;
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MPU_InitStruct.AccessPermission = MPU_REGION_FULL_ACCESS;
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MPU_InitStruct.IsBufferable = MPU_ACCESS_NOT_BUFFERABLE;
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MPU_InitStruct.IsCacheable = MPU_ACCESS_CACHEABLE;
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MPU_InitStruct.IsShareable = MPU_ACCESS_SHAREABLE;
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MPU_InitStruct.Number = MPU_REGION_NUMBER5;
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MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0;
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MPU_InitStruct.SubRegionDisable = 0x00;
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MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_DISABLE;
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HAL_MPU_ConfigRegion(&MPU_InitStruct);
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/* Enable MPU */
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HAL_MPU_Enable(MPU_PRIVILEGED_DEFAULT);
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}
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int main(void)
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{
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HAL_StatusTypeDef rc;
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SystemInit();
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rc = HAL_Init();
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if (rc != HAL_OK)
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{
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while(1) { ; }
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}
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#if 0 /* This is interfering with firmware boot after an update. It
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* appears that the data cache is getting in the way of the
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* reset handler properly copying over the data section into SRAM.
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*/
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SCB_EnableICache();
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SCB_EnableDCache();
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#endif
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SystemClock_Config();
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rng_setup();
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se_setup();
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/* Check for first-boot condition */
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if (!flash_is_programmed())
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flash_first_boot();
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/* Validate our pairing secret */
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if (!se_valid_secret(rom_secrets->pairing_secret))
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LOCKUP_FOREVER();
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/* Validate the internal firmware */
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if (!verify_current_firmware())
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LOCKUP_FOREVER();
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/* Check for firmware update */
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if (is_firmware_update_present())
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update_firmware();
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/* Setup MPU */
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MPU_Config();
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/* From here we'll boot to Micropython */
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}
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