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272 lines
9.9 KiB
272 lines
9.9 KiB
4 years ago
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/*
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Copyright (c) 2009-2018 ARM Limited. All rights reserved.
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SPDX-License-Identifier: Apache-2.0
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Licensed under the Apache License, Version 2.0 (the License); you may
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not use this file except in compliance with the License.
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You may obtain a copy of the License at
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www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an AS IS BASIS, WITHOUT
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WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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NOTICE: This file has been modified by Nordic Semiconductor ASA.
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*/
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/* NOTE: Template files (including this one) are application specific and therefore expected to
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be copied into the application project folder prior to its use! */
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#include <stdint.h>
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#include <stdbool.h>
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#include "nrf.h"
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#include "system_nrf9160.h"
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/*lint ++flb "Enter library region" */
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#define __SYSTEM_CLOCK (64000000UL) /*!< nRF9160 Application core uses a fixed System Clock Frequency of 64MHz */
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#define TRACE_PIN_CNF_VALUE ( (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos) | \
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(GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | \
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(GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos) | \
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(GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | \
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(GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos) | \
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(GPIO_PIN_CNF_MCUSEL_TND << GPIO_PIN_CNF_MCUSEL_Pos))
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#define TRACE_TRACECLK_PIN (21)
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#define TRACE_TRACEDATA0_PIN (22)
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#define TRACE_TRACEDATA1_PIN (23)
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#define TRACE_TRACEDATA2_PIN (24)
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#define TRACE_TRACEDATA3_PIN (25)
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#if defined ( __CC_ARM )
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uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK;
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#elif defined ( __ICCARM__ )
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__root uint32_t SystemCoreClock = __SYSTEM_CLOCK;
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#elif defined ( __GNUC__ )
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uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK;
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#endif
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/* Errata are only handled in secure mode since they usually need access to FICR. */
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#if !defined(NRF_TRUSTZONE_NONSECURE)
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static bool uicr_HFXOSRC_erased(void);
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static bool uicr_HFXOCNT_erased(void);
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static bool errata_6(void);
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static bool errata_14(void);
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static bool errata_15(void);
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static bool errata_20(void);
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#endif
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void SystemCoreClockUpdate(void)
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{
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SystemCoreClock = __SYSTEM_CLOCK;
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}
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void SystemInit(void)
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{
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#if !defined(NRF_TRUSTZONE_NONSECURE)
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/* Perform Secure-mode initialization routines. */
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/* Set all ARM SAU regions to NonSecure if TrustZone extensions are enabled.
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* Nordic SPU should handle Secure Attribution tasks */
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#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
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SAU->CTRL |= (1 << SAU_CTRL_ALLNS_Pos);
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#endif
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/* Trimming of the device. Copy all the trimming values from FICR into the target addresses. Trim
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until one ADDR is not initialized. */
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uint32_t index = 0;
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for (index = 0; index < 256ul && NRF_FICR_S->TRIMCNF[index].ADDR != 0xFFFFFFFFul; index++){
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#if defined ( __ICCARM__ )
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#pragma diag_suppress=Pa082
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#endif
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*(volatile uint32_t *)NRF_FICR_S->TRIMCNF[index].ADDR = NRF_FICR_S->TRIMCNF[index].DATA;
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#if defined ( __ICCARM__ )
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#pragma diag_default=Pa082
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#endif
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}
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/* Set UICR->HFXOSRC and UICR->HFXOCNT to working defaults if UICR was erased */
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if (uicr_HFXOSRC_erased() || uicr_HFXOCNT_erased()) {
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/* Wait for pending NVMC operations to finish */
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while (NRF_NVMC_S->READY != NVMC_READY_READY_Ready);
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/* Enable write mode in NVMC */
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NRF_NVMC_S->CONFIG = NVMC_CONFIG_WEN_Wen;
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while (NRF_NVMC_S->READY != NVMC_READY_READY_Ready);
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if (uicr_HFXOSRC_erased()){
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/* Write default value to UICR->HFXOSRC */
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NRF_UICR_S->HFXOSRC = (NRF_UICR_S->HFXOSRC & ~UICR_HFXOSRC_HFXOSRC_Msk) | UICR_HFXOSRC_HFXOSRC_TCXO;
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while (NRF_NVMC_S->READY != NVMC_READY_READY_Ready);
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}
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if (uicr_HFXOCNT_erased()){
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/* Write default value to UICR->HFXOCNT */
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NRF_UICR_S->HFXOCNT = (NRF_UICR_S->HFXOCNT & ~UICR_HFXOCNT_HFXOCNT_Msk) | 0x20;
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while (NRF_NVMC_S->READY != NVMC_READY_READY_Ready);
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}
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/* Enable read mode in NVMC */
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NRF_NVMC_S->CONFIG = NVMC_CONFIG_WEN_Ren;
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while (NRF_NVMC_S->READY != NVMC_READY_READY_Ready);
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/* Reset to apply clock select update */
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NVIC_SystemReset();
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}
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/* Workaround for Errata 6 "POWER: SLEEPENTER and SLEEPEXIT events asserted after pin reset" found at the Errata document
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for your device located at https://www.nordicsemi.com/DocLib */
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if (errata_6()){
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NRF_POWER_S->EVENTS_SLEEPENTER = (POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_NotGenerated << POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Pos);
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NRF_POWER_S->EVENTS_SLEEPEXIT = (POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_NotGenerated << POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Pos);
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}
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/* Workaround for Errata 14 "REGULATORS: LDO mode at startup" found at the Errata document
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for your device located at https://www.nordicsemi.com/DocLib */
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if (errata_14()){
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*((volatile uint32_t *)0x50004A38) = 0x01ul;
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NRF_REGULATORS_S->DCDCEN = REGULATORS_DCDCEN_DCDCEN_Enabled << REGULATORS_DCDCEN_DCDCEN_Pos;
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}
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/* Workaround for Errata 15 "REGULATORS: LDO mode at startup" found at the Errata document
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for your device located at https://www.nordicsemi.com/DocLib */
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if (errata_15()){
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*((volatile uint32_t *)0x50004A38) = 0x00ul;
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NRF_REGULATORS_S->DCDCEN = REGULATORS_DCDCEN_DCDCEN_Enabled << REGULATORS_DCDCEN_DCDCEN_Pos;
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}
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/* Workaround for Errata 20 "RAM content cannot be trusted upon waking up from System ON Idle or System OFF mode" found at the Errata document
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for your device located at https://www.nordicsemi.com/DocLib */
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if (errata_20()){
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*((volatile uint32_t *)0x5003AEE4) = 0xC;
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}
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/* Enable SWO trace functionality. If ENABLE_SWO is not defined, SWO pin will be used as GPIO (see Product
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Specification to see which one). */
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#if defined (ENABLE_SWO)
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NRF_TAD_S->ENABLE = TAD_ENABLE_ENABLE_Msk;
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NRF_TAD_S->CLOCKSTART = TAD_CLOCKSTART_START_Msk;
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NRF_TAD_S->PSEL.TRACEDATA0 = TRACE_TRACEDATA0_PIN;
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NRF_TAD_S->TRACEPORTSPEED = TAD_TRACEPORTSPEED_TRACEPORTSPEED_32MHz;
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NRF_P0_S->PIN_CNF[TRACE_TRACEDATA0_PIN] = TRACE_PIN_CNF_VALUE;
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#endif
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/* Enable Trace functionality. If ENABLE_TRACE is not defined, TRACE pins will be used as GPIOs (see Product
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Specification to see which ones). */
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#if defined (ENABLE_TRACE)
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NRF_TAD_S->ENABLE = TAD_ENABLE_ENABLE_Msk;
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NRF_TAD_S->CLOCKSTART = TAD_CLOCKSTART_START_Msk;
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NRF_TAD_S->PSEL.TRACECLK = TRACE_TRACECLK_PIN;
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NRF_TAD_S->PSEL.TRACEDATA0 = TRACE_TRACEDATA0_PIN;
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NRF_TAD_S->PSEL.TRACEDATA1 = TRACE_TRACEDATA1_PIN;
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NRF_TAD_S->PSEL.TRACEDATA2 = TRACE_TRACEDATA2_PIN;
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NRF_TAD_S->PSEL.TRACEDATA3 = TRACE_TRACEDATA3_PIN;
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NRF_TAD_S->TRACEPORTSPEED = TAD_TRACEPORTSPEED_TRACEPORTSPEED_32MHz;
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NRF_P0_S->PIN_CNF[TRACE_TRACECLK_PIN] = TRACE_PIN_CNF_VALUE;
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NRF_P0_S->PIN_CNF[TRACE_TRACEDATA0_PIN] = TRACE_PIN_CNF_VALUE;
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NRF_P0_S->PIN_CNF[TRACE_TRACEDATA1_PIN] = TRACE_PIN_CNF_VALUE;
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NRF_P0_S->PIN_CNF[TRACE_TRACEDATA2_PIN] = TRACE_PIN_CNF_VALUE;
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NRF_P0_S->PIN_CNF[TRACE_TRACEDATA3_PIN] = TRACE_PIN_CNF_VALUE;
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#endif
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/* Allow Non-Secure code to run FPU instructions.
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* If only the secure code should control FPU power state these registers should be configured accordingly in the secure application code. */
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SCB->NSACR |= (3UL << 10);
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#endif
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/* Enable the FPU if the compiler used floating point unit instructions. __FPU_USED is a MACRO defined by the
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* compiler. Since the FPU consumes energy, remember to disable FPU use in the compiler if floating point unit
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* operations are not used in your code. */
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#if (__FPU_USED == 1)
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SCB->CPACR |= (3UL << 20) | (3UL << 22);
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__DSB();
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__ISB();
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#endif
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SystemCoreClockUpdate();
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}
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#if !defined(NRF_TRUSTZONE_NONSECURE)
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bool uicr_HFXOCNT_erased()
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{
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if (NRF_UICR_S->HFXOCNT == 0xFFFFFFFFul) {
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return true;
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}
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return false;
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}
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bool uicr_HFXOSRC_erased()
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{
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if ((NRF_UICR_S->HFXOSRC & UICR_HFXOSRC_HFXOSRC_Msk) != UICR_HFXOSRC_HFXOSRC_TCXO) {
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return true;
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}
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return false;
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}
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bool errata_6()
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{
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if (*(uint32_t *)0x00FF0130 == 0x9ul){
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if (*(uint32_t *)0x00FF0134 == 0x01ul){
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return true;
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}
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if (*(uint32_t *)0x00FF0134 == 0x02ul){
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return true;
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}
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}
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return false;
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}
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bool errata_14()
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{
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if (*(uint32_t *)0x00FF0130 == 0x9ul){
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if (*(uint32_t *)0x00FF0134 == 0x01ul){
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return true;
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}
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}
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return false;
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}
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bool errata_15()
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{
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if (*(uint32_t *)0x00FF0130 == 0x9ul){
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if (*(uint32_t *)0x00FF0134 == 0x02ul){
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return true;
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}
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}
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return false;
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}
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bool errata_20()
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{
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if (*(uint32_t *)0x00FF0130 == 0x9ul){
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if (*(uint32_t *)0x00FF0134 == 0x02ul){
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return true;
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}
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}
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return false;
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}
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#endif
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/*lint --flb "Leave library region" */
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