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628 lines
23 KiB
628 lines
23 KiB
/*
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* Copyright (c) 2015 - 2019, Nordic Semiconductor ASA
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef NRF_UARTE_H__
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#define NRF_UARTE_H__
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#include <nrfx.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define NRF_UARTE_PSEL_DISCONNECTED 0xFFFFFFFF
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/**
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* @defgroup nrf_uarte_hal UARTE HAL
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* @{
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* @ingroup nrf_uarte
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* @brief Hardware access layer for managing the UARTE peripheral.
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*/
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/** @brief UARTE tasks. */
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typedef enum
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{
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NRF_UARTE_TASK_STARTRX = offsetof(NRF_UARTE_Type, TASKS_STARTRX), ///< Start UART receiver.
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NRF_UARTE_TASK_STOPRX = offsetof(NRF_UARTE_Type, TASKS_STOPRX), ///< Stop UART receiver.
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NRF_UARTE_TASK_STARTTX = offsetof(NRF_UARTE_Type, TASKS_STARTTX), ///< Start UART transmitter.
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NRF_UARTE_TASK_STOPTX = offsetof(NRF_UARTE_Type, TASKS_STOPTX), ///< Stop UART transmitter.
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NRF_UARTE_TASK_FLUSHRX = offsetof(NRF_UARTE_Type, TASKS_FLUSHRX) ///< Flush RX FIFO in RX buffer.
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} nrf_uarte_task_t;
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/** @brief UARTE events. */
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typedef enum
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{
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NRF_UARTE_EVENT_CTS = offsetof(NRF_UARTE_Type, EVENTS_CTS), ///< CTS is activated.
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NRF_UARTE_EVENT_NCTS = offsetof(NRF_UARTE_Type, EVENTS_NCTS), ///< CTS is deactivated.
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NRF_UARTE_EVENT_RXDRDY = offsetof(NRF_UARTE_Type, EVENTS_RXDRDY), ///< Data received in RXD (but potentially not yet transferred to Data RAM).
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NRF_UARTE_EVENT_ENDRX = offsetof(NRF_UARTE_Type, EVENTS_ENDRX), ///< Receive buffer is filled up.
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NRF_UARTE_EVENT_TXDRDY = offsetof(NRF_UARTE_Type, EVENTS_TXDRDY), ///< Data sent from TXD.
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NRF_UARTE_EVENT_ENDTX = offsetof(NRF_UARTE_Type, EVENTS_ENDTX), ///< Last TX byte transmitted.
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NRF_UARTE_EVENT_ERROR = offsetof(NRF_UARTE_Type, EVENTS_ERROR), ///< Error detected.
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NRF_UARTE_EVENT_RXTO = offsetof(NRF_UARTE_Type, EVENTS_RXTO), ///< Receiver timeout.
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NRF_UARTE_EVENT_RXSTARTED = offsetof(NRF_UARTE_Type, EVENTS_RXSTARTED), ///< Receiver has started.
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NRF_UARTE_EVENT_TXSTARTED = offsetof(NRF_UARTE_Type, EVENTS_TXSTARTED), ///< Transmitter has started.
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NRF_UARTE_EVENT_TXSTOPPED = offsetof(NRF_UARTE_Type, EVENTS_TXSTOPPED) ///< Transmitted stopped.
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} nrf_uarte_event_t;
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/** @brief Types of UARTE shortcuts. */
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typedef enum
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{
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NRF_UARTE_SHORT_ENDRX_STARTRX = UARTE_SHORTS_ENDRX_STARTRX_Msk, ///< Shortcut between ENDRX event and STARTRX task.
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NRF_UARTE_SHORT_ENDRX_STOPRX = UARTE_SHORTS_ENDRX_STOPRX_Msk ///< Shortcut between ENDRX event and STOPRX task.
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} nrf_uarte_short_t;
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/** @brief UARTE interrupts. */
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typedef enum
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{
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NRF_UARTE_INT_CTS_MASK = UARTE_INTENSET_CTS_Msk, ///< Interrupt on CTS event.
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NRF_UARTE_INT_NCTS_MASK = UARTE_INTENSET_NCTS_Msk, ///< Interrupt on NCTS event.
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NRF_UARTE_INT_RXDRDY_MASK = UARTE_INTENSET_RXDRDY_Msk, ///< Interrupt on RXDRDY event.
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NRF_UARTE_INT_ENDRX_MASK = UARTE_INTENSET_ENDRX_Msk, ///< Interrupt on ENDRX event.
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NRF_UARTE_INT_TXDRDY_MASK = UARTE_INTENSET_TXDRDY_Msk, ///< Interrupt on TXDRDY event.
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NRF_UARTE_INT_ENDTX_MASK = UARTE_INTENSET_ENDTX_Msk, ///< Interrupt on ENDTX event.
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NRF_UARTE_INT_ERROR_MASK = UARTE_INTENSET_ERROR_Msk, ///< Interrupt on ERROR event.
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NRF_UARTE_INT_RXTO_MASK = UARTE_INTENSET_RXTO_Msk, ///< Interrupt on RXTO event.
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NRF_UARTE_INT_RXSTARTED_MASK = UARTE_INTENSET_RXSTARTED_Msk, ///< Interrupt on RXSTARTED event.
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NRF_UARTE_INT_TXSTARTED_MASK = UARTE_INTENSET_TXSTARTED_Msk, ///< Interrupt on TXSTARTED event.
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NRF_UARTE_INT_TXSTOPPED_MASK = UARTE_INTENSET_TXSTOPPED_Msk ///< Interrupt on TXSTOPPED event.
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} nrf_uarte_int_mask_t;
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/** @brief Baudrates supported by UARTE. */
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typedef enum
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{
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NRF_UARTE_BAUDRATE_1200 = UARTE_BAUDRATE_BAUDRATE_Baud1200, ///< 1200 baud.
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NRF_UARTE_BAUDRATE_2400 = UARTE_BAUDRATE_BAUDRATE_Baud2400, ///< 2400 baud.
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NRF_UARTE_BAUDRATE_4800 = UARTE_BAUDRATE_BAUDRATE_Baud4800, ///< 4800 baud.
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NRF_UARTE_BAUDRATE_9600 = UARTE_BAUDRATE_BAUDRATE_Baud9600, ///< 9600 baud.
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NRF_UARTE_BAUDRATE_14400 = UARTE_BAUDRATE_BAUDRATE_Baud14400, ///< 14400 baud.
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NRF_UARTE_BAUDRATE_19200 = UARTE_BAUDRATE_BAUDRATE_Baud19200, ///< 19200 baud.
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NRF_UARTE_BAUDRATE_28800 = UARTE_BAUDRATE_BAUDRATE_Baud28800, ///< 28800 baud.
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NRF_UARTE_BAUDRATE_31250 = UARTE_BAUDRATE_BAUDRATE_Baud31250, ///< 31250 baud.
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NRF_UARTE_BAUDRATE_38400 = UARTE_BAUDRATE_BAUDRATE_Baud38400, ///< 38400 baud.
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NRF_UARTE_BAUDRATE_56000 = UARTE_BAUDRATE_BAUDRATE_Baud56000, ///< 56000 baud.
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NRF_UARTE_BAUDRATE_57600 = UARTE_BAUDRATE_BAUDRATE_Baud57600, ///< 57600 baud.
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NRF_UARTE_BAUDRATE_76800 = UARTE_BAUDRATE_BAUDRATE_Baud76800, ///< 76800 baud.
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NRF_UARTE_BAUDRATE_115200 = UARTE_BAUDRATE_BAUDRATE_Baud115200, ///< 115200 baud.
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NRF_UARTE_BAUDRATE_230400 = UARTE_BAUDRATE_BAUDRATE_Baud230400, ///< 230400 baud.
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NRF_UARTE_BAUDRATE_250000 = UARTE_BAUDRATE_BAUDRATE_Baud250000, ///< 250000 baud.
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NRF_UARTE_BAUDRATE_460800 = UARTE_BAUDRATE_BAUDRATE_Baud460800, ///< 460800 baud.
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NRF_UARTE_BAUDRATE_921600 = UARTE_BAUDRATE_BAUDRATE_Baud921600, ///< 921600 baud.
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NRF_UARTE_BAUDRATE_1000000 = UARTE_BAUDRATE_BAUDRATE_Baud1M ///< 1000000 baud.
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} nrf_uarte_baudrate_t;
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/** @brief Types of UARTE error masks. */
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typedef enum
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{
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NRF_UARTE_ERROR_OVERRUN_MASK = UARTE_ERRORSRC_OVERRUN_Msk, ///< Overrun error.
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NRF_UARTE_ERROR_PARITY_MASK = UARTE_ERRORSRC_PARITY_Msk, ///< Parity error.
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NRF_UARTE_ERROR_FRAMING_MASK = UARTE_ERRORSRC_FRAMING_Msk, ///< Framing error.
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NRF_UARTE_ERROR_BREAK_MASK = UARTE_ERRORSRC_BREAK_Msk ///< Break error.
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} nrf_uarte_error_mask_t;
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/** @brief Types of UARTE parity modes. */
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typedef enum
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{
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NRF_UARTE_PARITY_EXCLUDED = UARTE_CONFIG_PARITY_Excluded << UARTE_CONFIG_PARITY_Pos, ///< Parity excluded.
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NRF_UARTE_PARITY_INCLUDED = UARTE_CONFIG_PARITY_Included << UARTE_CONFIG_PARITY_Pos ///< Parity included.
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} nrf_uarte_parity_t;
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/** @brief Types of UARTE flow control modes. */
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typedef enum
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{
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NRF_UARTE_HWFC_DISABLED = UARTE_CONFIG_HWFC_Disabled << UARTE_CONFIG_HWFC_Pos, ///< Hardware flow control disabled.
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NRF_UARTE_HWFC_ENABLED = UARTE_CONFIG_HWFC_Enabled << UARTE_CONFIG_HWFC_Pos ///< Hardware flow control enabled.
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} nrf_uarte_hwfc_t;
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/**
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* @brief Function for clearing the specified UARTE event.
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*
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* @param[in] p_reg Pointer to the structure of registers of the peripheral.
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* @param[in] event Event to clear.
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*/
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__STATIC_INLINE void nrf_uarte_event_clear(NRF_UARTE_Type * p_reg, nrf_uarte_event_t event);
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/**
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* @brief Function for retrieving the state of the UARTE event.
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*
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* @param[in] p_reg Pointer to the structure of registers of the peripheral.
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* @param[in] event Event to be checked.
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*
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* @retval true The event has been generated.
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* @retval false The event has not been generated.
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*/
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__STATIC_INLINE bool nrf_uarte_event_check(NRF_UARTE_Type * p_reg, nrf_uarte_event_t event);
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/**
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* @brief Function for returning the address of the specified UARTE event register.
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*
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* @param[in] p_reg Pointer to the structure of registers of the peripheral.
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* @param[in] event The specified event.
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*
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* @return Address of specified event register.
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*/
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__STATIC_INLINE uint32_t nrf_uarte_event_address_get(NRF_UARTE_Type * p_reg,
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nrf_uarte_event_t event);
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/**
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* @brief Function for enabling UARTE shortcuts.
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*
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* @param p_reg Pointer to the structure of registers of the peripheral.
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* @param mask Shortcuts to be enabled.
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*/
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__STATIC_INLINE void nrf_uarte_shorts_enable(NRF_UARTE_Type * p_reg, uint32_t mask);
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/**
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* @brief Function for disabling UARTE shortcuts.
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*
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* @param p_reg Pointer to the structure of registers of the peripheral.
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* @param mask Shortcuts to be disabled.
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*/
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__STATIC_INLINE void nrf_uarte_shorts_disable(NRF_UARTE_Type * p_reg, uint32_t mask);
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/**
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* @brief Function for enabling UARTE interrupts.
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*
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* @param p_reg Pointer to the structure of registers of the peripheral.
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* @param mask Mask of interrupts to be enabled.
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*/
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__STATIC_INLINE void nrf_uarte_int_enable(NRF_UARTE_Type * p_reg, uint32_t mask);
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/**
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* @brief Function for retrieving the state of the specified interrupt.
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*
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* @param p_reg Pointer to the structure of registers of the peripheral.
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* @param mask Mask of interrupts to be checked.
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*
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* @retval true The interrupt is enabled.
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* @retval false The interrupt is not enabled.
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*/
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__STATIC_INLINE bool nrf_uarte_int_enable_check(NRF_UARTE_Type * p_reg, nrf_uarte_int_mask_t mask);
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/**
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* @brief Function for disabling the specified interrupts.
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*
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* @param p_reg Pointer to the structure of registers of the peripheral.
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* @param mask Mask of interrupts to be disabled.
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*/
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__STATIC_INLINE void nrf_uarte_int_disable(NRF_UARTE_Type * p_reg, uint32_t mask);
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#if defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__)
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/**
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* @brief Function for setting the subscribe configuration for a given
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* UARTE task.
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*
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* @param[in] p_reg Pointer to the structure of registers of the peripheral.
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* @param[in] task Task for which to set the configuration.
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* @param[in] channel Channel through which to subscribe events.
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*/
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__STATIC_INLINE void nrf_uarte_subscribe_set(NRF_UARTE_Type * p_reg,
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nrf_uarte_task_t task,
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uint8_t channel);
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/**
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* @brief Function for clearing the subscribe configuration for a given
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* UARTE task.
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*
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* @param[in] p_reg Pointer to the structure of registers of the peripheral.
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* @param[in] task Task for which to clear the configuration.
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*/
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__STATIC_INLINE void nrf_uarte_subscribe_clear(NRF_UARTE_Type * p_reg,
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nrf_uarte_task_t task);
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/**
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* @brief Function for setting the publish configuration for a given
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* UARTE event.
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*
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* @param[in] p_reg Pointer to the structure of registers of the peripheral.
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* @param[in] event Event for which to set the configuration.
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* @param[in] channel Channel through which to publish the event.
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*/
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__STATIC_INLINE void nrf_uarte_publish_set(NRF_UARTE_Type * p_reg,
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nrf_uarte_event_t event,
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uint8_t channel);
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/**
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* @brief Function for clearing the publish configuration for a given
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* UARTE event.
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*
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* @param[in] p_reg Pointer to the structure of registers of the peripheral.
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* @param[in] event Event for which to clear the configuration.
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*/
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__STATIC_INLINE void nrf_uarte_publish_clear(NRF_UARTE_Type * p_reg,
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nrf_uarte_event_t event);
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#endif // defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__)
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/**
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* @brief Function for getting error source mask. Function is clearing error source flags after reading.
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*
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* @param p_reg Pointer to the structure of registers of the peripheral.
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*
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* @return Mask with error source flags.
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*/
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__STATIC_INLINE uint32_t nrf_uarte_errorsrc_get_and_clear(NRF_UARTE_Type * p_reg);
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/**
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* @brief Function for enabling UARTE.
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*
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* @param p_reg Pointer to the structure of registers of the peripheral.
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*/
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__STATIC_INLINE void nrf_uarte_enable(NRF_UARTE_Type * p_reg);
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/**
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* @brief Function for disabling UARTE.
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*
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* @param p_reg Pointer to the structure of registers of the peripheral.
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*/
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__STATIC_INLINE void nrf_uarte_disable(NRF_UARTE_Type * p_reg);
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/**
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* @brief Function for configuring TX/RX pins.
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*
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* @param p_reg Pointer to the structure of registers of the peripheral.
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* @param pseltxd TXD pin number.
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* @param pselrxd RXD pin number.
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*/
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__STATIC_INLINE void nrf_uarte_txrx_pins_set(NRF_UARTE_Type * p_reg,
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uint32_t pseltxd,
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uint32_t pselrxd);
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/**
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* @brief Function for disconnecting TX/RX pins.
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*
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* @param p_reg Pointer to the structure of registers of the peripheral.
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*/
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__STATIC_INLINE void nrf_uarte_txrx_pins_disconnect(NRF_UARTE_Type * p_reg);
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/**
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* @brief Function for getting TX pin.
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*
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* @param p_reg Pointer to the structure of registers of the peripheral.
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*
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* @return TX pin number.
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*/
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__STATIC_INLINE uint32_t nrf_uarte_tx_pin_get(NRF_UARTE_Type * p_reg);
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/**
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* @brief Function for getting RX pin.
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*
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* @param p_reg Pointer to the structure of registers of the peripheral.
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*
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* @return RX pin number.
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*/
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__STATIC_INLINE uint32_t nrf_uarte_rx_pin_get(NRF_UARTE_Type * p_reg);
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/**
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* @brief Function for getting RTS pin.
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*
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* @param p_reg Pointer to the structure of registers of the peripheral.
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*
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* @return RTS pin number.
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*/
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__STATIC_INLINE uint32_t nrf_uarte_rts_pin_get(NRF_UARTE_Type * p_reg);
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/**
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* @brief Function for getting CTS pin.
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*
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* @param p_reg Pointer to the structure of registers of the peripheral.
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*
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* @return CTS pin number.
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*/
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__STATIC_INLINE uint32_t nrf_uarte_cts_pin_get(NRF_UARTE_Type * p_reg);
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/**
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* @brief Function for configuring flow control pins.
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*
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* @param p_reg Pointer to the structure of registers of the peripheral.
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* @param pselrts RTS pin number.
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* @param pselcts CTS pin number.
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*/
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__STATIC_INLINE void nrf_uarte_hwfc_pins_set(NRF_UARTE_Type * p_reg,
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uint32_t pselrts,
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uint32_t pselcts);
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/**
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* @brief Function for disconnecting flow control pins.
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*
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* @param p_reg Pointer to the structure of registers of the peripheral.
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*/
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__STATIC_INLINE void nrf_uarte_hwfc_pins_disconnect(NRF_UARTE_Type * p_reg);
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/**
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* @brief Function for starting an UARTE task.
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*
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* @param p_reg Pointer to the structure of registers of the peripheral.
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* @param task Task.
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*/
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__STATIC_INLINE void nrf_uarte_task_trigger(NRF_UARTE_Type * p_reg, nrf_uarte_task_t task);
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/**
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* @brief Function for returning the address of the specified task register.
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*
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* @param p_reg Pointer to the structure of registers of the peripheral.
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* @param task Task.
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*
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* @return Task address.
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*/
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__STATIC_INLINE uint32_t nrf_uarte_task_address_get(NRF_UARTE_Type * p_reg, nrf_uarte_task_t task);
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/**
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* @brief Function for configuring UARTE.
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*
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* @param p_reg Pointer to the structure of registers of the peripheral.
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* @param hwfc Hardware flow control. Enabled if true.
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* @param parity Parity. Included if true.
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*/
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__STATIC_INLINE void nrf_uarte_configure(NRF_UARTE_Type * p_reg,
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nrf_uarte_parity_t parity,
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nrf_uarte_hwfc_t hwfc);
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/**
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* @brief Function for setting UARTE baud rate.
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*
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* @param p_reg Pointer to the structure of registers of the peripheral.
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* @param baudrate Baud rate.
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*/
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__STATIC_INLINE void nrf_uarte_baudrate_set(NRF_UARTE_Type * p_reg, nrf_uarte_baudrate_t baudrate);
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/**
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|
* @brief Function for setting the transmit buffer.
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*
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* @param[in] p_reg Pointer to the structure of registers of the peripheral.
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* @param[in] p_buffer Pointer to the buffer with data to send.
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* @param[in] length Maximum number of data bytes to transmit.
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*/
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__STATIC_INLINE void nrf_uarte_tx_buffer_set(NRF_UARTE_Type * p_reg,
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uint8_t const * p_buffer,
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size_t length);
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/**
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* @brief Function for getting number of bytes transmitted in the last transaction.
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*
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* @param[in] p_reg Pointer to the structure of registers of the peripheral.
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*
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* @retval Amount of bytes transmitted.
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*/
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__STATIC_INLINE uint32_t nrf_uarte_tx_amount_get(NRF_UARTE_Type * p_reg);
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/**
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|
* @brief Function for setting the receive buffer.
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*
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* @param[in] p_reg Pointer to the structure of registers of the peripheral.
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* @param[in] p_buffer Pointer to the buffer for received data.
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* @param[in] length Maximum number of data bytes to receive.
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|
*/
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__STATIC_INLINE void nrf_uarte_rx_buffer_set(NRF_UARTE_Type * p_reg,
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uint8_t * p_buffer,
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|
size_t length);
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/**
|
|
* @brief Function for getting number of bytes received in the last transaction.
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|
*
|
|
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
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*
|
|
* @retval Amount of bytes received.
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|
*/
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__STATIC_INLINE uint32_t nrf_uarte_rx_amount_get(NRF_UARTE_Type * p_reg);
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#ifndef SUPPRESS_INLINE_IMPLEMENTATION
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__STATIC_INLINE void nrf_uarte_event_clear(NRF_UARTE_Type * p_reg, nrf_uarte_event_t event)
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|
{
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*((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
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#if __CORTEX_M == 0x04
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volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event));
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(void)dummy;
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#endif
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}
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__STATIC_INLINE bool nrf_uarte_event_check(NRF_UARTE_Type * p_reg, nrf_uarte_event_t event)
|
|
{
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|
return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
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}
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|
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__STATIC_INLINE uint32_t nrf_uarte_event_address_get(NRF_UARTE_Type * p_reg,
|
|
nrf_uarte_event_t event)
|
|
{
|
|
return (uint32_t)((uint8_t *)p_reg + (uint32_t)event);
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|
}
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__STATIC_INLINE void nrf_uarte_shorts_enable(NRF_UARTE_Type * p_reg, uint32_t mask)
|
|
{
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|
p_reg->SHORTS |= mask;
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|
}
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|
__STATIC_INLINE void nrf_uarte_shorts_disable(NRF_UARTE_Type * p_reg, uint32_t mask)
|
|
{
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|
p_reg->SHORTS &= ~(mask);
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|
}
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|
|
|
__STATIC_INLINE void nrf_uarte_int_enable(NRF_UARTE_Type * p_reg, uint32_t mask)
|
|
{
|
|
p_reg->INTENSET = mask;
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|
}
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|
|
|
__STATIC_INLINE bool nrf_uarte_int_enable_check(NRF_UARTE_Type * p_reg, nrf_uarte_int_mask_t mask)
|
|
{
|
|
return (bool)(p_reg->INTENSET & mask);
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|
}
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|
|
|
__STATIC_INLINE void nrf_uarte_int_disable(NRF_UARTE_Type * p_reg, uint32_t mask)
|
|
{
|
|
p_reg->INTENCLR = mask;
|
|
}
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|
|
|
#if defined(DPPI_PRESENT)
|
|
__STATIC_INLINE void nrf_uarte_subscribe_set(NRF_UARTE_Type * p_reg,
|
|
nrf_uarte_task_t task,
|
|
uint8_t channel)
|
|
{
|
|
*((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) =
|
|
((uint32_t)channel | UARTE_SUBSCRIBE_STARTRX_EN_Msk);
|
|
}
|
|
|
|
__STATIC_INLINE void nrf_uarte_subscribe_clear(NRF_UARTE_Type * p_reg,
|
|
nrf_uarte_task_t task)
|
|
{
|
|
*((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) = 0;
|
|
}
|
|
|
|
__STATIC_INLINE void nrf_uarte_publish_set(NRF_UARTE_Type * p_reg,
|
|
nrf_uarte_event_t event,
|
|
uint8_t channel)
|
|
{
|
|
*((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) event + 0x80uL)) =
|
|
((uint32_t)channel | UARTE_PUBLISH_CTS_EN_Msk);
|
|
}
|
|
|
|
__STATIC_INLINE void nrf_uarte_publish_clear(NRF_UARTE_Type * p_reg,
|
|
nrf_uarte_event_t event)
|
|
{
|
|
*((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) event + 0x80uL)) = 0;
|
|
}
|
|
#endif // defined(DPPI_PRESENT)
|
|
|
|
__STATIC_INLINE uint32_t nrf_uarte_errorsrc_get_and_clear(NRF_UARTE_Type * p_reg)
|
|
{
|
|
uint32_t errsrc_mask = p_reg->ERRORSRC;
|
|
p_reg->ERRORSRC = errsrc_mask;
|
|
return errsrc_mask;
|
|
}
|
|
|
|
__STATIC_INLINE void nrf_uarte_enable(NRF_UARTE_Type * p_reg)
|
|
{
|
|
p_reg->ENABLE = UARTE_ENABLE_ENABLE_Enabled;
|
|
}
|
|
|
|
__STATIC_INLINE void nrf_uarte_disable(NRF_UARTE_Type * p_reg)
|
|
{
|
|
p_reg->ENABLE = UARTE_ENABLE_ENABLE_Disabled;
|
|
}
|
|
|
|
__STATIC_INLINE void nrf_uarte_txrx_pins_set(NRF_UARTE_Type * p_reg, uint32_t pseltxd, uint32_t pselrxd)
|
|
{
|
|
p_reg->PSEL.TXD = pseltxd;
|
|
p_reg->PSEL.RXD = pselrxd;
|
|
}
|
|
|
|
__STATIC_INLINE void nrf_uarte_txrx_pins_disconnect(NRF_UARTE_Type * p_reg)
|
|
{
|
|
nrf_uarte_txrx_pins_set(p_reg, NRF_UARTE_PSEL_DISCONNECTED, NRF_UARTE_PSEL_DISCONNECTED);
|
|
}
|
|
|
|
__STATIC_INLINE uint32_t nrf_uarte_tx_pin_get(NRF_UARTE_Type * p_reg)
|
|
{
|
|
return p_reg->PSEL.TXD;
|
|
}
|
|
|
|
__STATIC_INLINE uint32_t nrf_uarte_rx_pin_get(NRF_UARTE_Type * p_reg)
|
|
{
|
|
return p_reg->PSEL.RXD;
|
|
}
|
|
|
|
__STATIC_INLINE uint32_t nrf_uarte_rts_pin_get(NRF_UARTE_Type * p_reg)
|
|
{
|
|
return p_reg->PSEL.RTS;
|
|
}
|
|
|
|
__STATIC_INLINE uint32_t nrf_uarte_cts_pin_get(NRF_UARTE_Type * p_reg)
|
|
{
|
|
return p_reg->PSEL.CTS;
|
|
}
|
|
|
|
__STATIC_INLINE void nrf_uarte_hwfc_pins_set(NRF_UARTE_Type * p_reg, uint32_t pselrts, uint32_t pselcts)
|
|
{
|
|
p_reg->PSEL.RTS = pselrts;
|
|
p_reg->PSEL.CTS = pselcts;
|
|
}
|
|
|
|
__STATIC_INLINE void nrf_uarte_hwfc_pins_disconnect(NRF_UARTE_Type * p_reg)
|
|
{
|
|
nrf_uarte_hwfc_pins_set(p_reg, NRF_UARTE_PSEL_DISCONNECTED, NRF_UARTE_PSEL_DISCONNECTED);
|
|
}
|
|
|
|
__STATIC_INLINE void nrf_uarte_task_trigger(NRF_UARTE_Type * p_reg, nrf_uarte_task_t task)
|
|
{
|
|
*((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
|
|
}
|
|
|
|
__STATIC_INLINE uint32_t nrf_uarte_task_address_get(NRF_UARTE_Type * p_reg, nrf_uarte_task_t task)
|
|
{
|
|
return (uint32_t)p_reg + (uint32_t)task;
|
|
}
|
|
|
|
__STATIC_INLINE void nrf_uarte_configure(NRF_UARTE_Type * p_reg,
|
|
nrf_uarte_parity_t parity,
|
|
nrf_uarte_hwfc_t hwfc)
|
|
{
|
|
p_reg->CONFIG = (uint32_t)parity | (uint32_t)hwfc;
|
|
}
|
|
|
|
__STATIC_INLINE void nrf_uarte_baudrate_set(NRF_UARTE_Type * p_reg, nrf_uarte_baudrate_t baudrate)
|
|
{
|
|
p_reg->BAUDRATE = baudrate;
|
|
}
|
|
|
|
__STATIC_INLINE void nrf_uarte_tx_buffer_set(NRF_UARTE_Type * p_reg,
|
|
uint8_t const * p_buffer,
|
|
size_t length)
|
|
{
|
|
p_reg->TXD.PTR = (uint32_t)p_buffer;
|
|
p_reg->TXD.MAXCNT = length;
|
|
}
|
|
|
|
__STATIC_INLINE uint32_t nrf_uarte_tx_amount_get(NRF_UARTE_Type * p_reg)
|
|
{
|
|
return p_reg->TXD.AMOUNT;
|
|
}
|
|
|
|
__STATIC_INLINE void nrf_uarte_rx_buffer_set(NRF_UARTE_Type * p_reg,
|
|
uint8_t * p_buffer,
|
|
size_t length)
|
|
{
|
|
p_reg->RXD.PTR = (uint32_t)p_buffer;
|
|
p_reg->RXD.MAXCNT = length;
|
|
}
|
|
|
|
__STATIC_INLINE uint32_t nrf_uarte_rx_amount_get(NRF_UARTE_Type * p_reg)
|
|
{
|
|
return p_reg->RXD.AMOUNT;
|
|
}
|
|
#endif //SUPPRESS_INLINE_IMPLEMENTATION
|
|
|
|
/** @} */
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
|
#endif //NRF_UARTE_H__
|
|
|