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441 lines
19 KiB
441 lines
19 KiB
/*
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* Copyright (c) 2018 - 2019, Nordic Semiconductor ASA
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef NRF_SPU_H__
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#define NRF_SPU_H__
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#include <nrfx.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @defgroup nrf_spu_hal SPU HAL
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* @{
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* @ingroup nrf_spu
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* @brief Hardware access layer for managing the System Protection Unit (SPU) peripheral.
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*/
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/** @brief SPU events. */
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typedef enum
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{
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NRF_SPU_EVENT_RAMACCERR = offsetof(NRF_SPU_Type, EVENTS_RAMACCERR), ///< A security violation has been detected for the RAM memory space.
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NRF_SPU_EVENT_FLASHACCERR = offsetof(NRF_SPU_Type, EVENTS_FLASHACCERR), ///< A security violation has been detected for the Flash memory space.
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NRF_SPU_EVENT_PERIPHACCERR = offsetof(NRF_SPU_Type, EVENTS_PERIPHACCERR) ///< A security violation has been detected on one or several peripherals.
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} nrf_spu_event_t;
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/** @brief SPU interrupts. */
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typedef enum
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{
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NRF_SPU_INT_RAMACCERR_MASK = SPU_INTENSET_RAMACCERR_Msk, ///< Interrupt on RAMACCERR event.
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NRF_SPU_INT_FLASHACCERR_MASK = SPU_INTENSET_FLASHACCERR_Msk, ///< Interrupt on FLASHACCERR event.
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NRF_SPU_INT_PERIPHACCERR_MASK = SPU_INTENSET_PERIPHACCERR_Msk ///< Interrupt on PERIPHACCERR event.
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} nrf_spu_int_mask_t;
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/** @brief SPU Non-Secure Callable (NSC) region size. */
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typedef enum
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{
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NRF_SPU_NSC_SIZE_DISABLED = 0, ///< Not defined as a non-secure callable region.
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NRF_SPU_NSC_SIZE_32B = 1, ///< Non-Secure Callable region with a 32-byte size
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NRF_SPU_NSC_SIZE_64B = 2, ///< Non-Secure Callable region with a 64-byte size
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NRF_SPU_NSC_SIZE_128B = 3, ///< Non-Secure Callable region with a 128-byte size
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NRF_SPU_NSC_SIZE_256B = 4, ///< Non-Secure Callable region with a 256-byte size
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NRF_SPU_NSC_SIZE_512B = 5, ///< Non-Secure Callable region with a 512-byte size
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NRF_SPU_NSC_SIZE_1024B = 6, ///< Non-Secure Callable region with a 1024-byte size
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NRF_SPU_NSC_SIZE_2048B = 7, ///< Non-Secure Callable region with a 2048-byte size
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NRF_SPU_NSC_SIZE_4096B = 8 ///< Non-Secure Callable region with a 4096-byte size
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} nrf_spu_nsc_size_t;
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/** @brief SPU memory region permissions. */
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typedef enum
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{
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NRF_SPU_MEM_PERM_EXECUTE = SPU_FLASHREGION_PERM_EXECUTE_Msk, ///< Allow code execution from particular memory region.
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NRF_SPU_MEM_PERM_WRITE = SPU_FLASHREGION_PERM_WRITE_Msk, ///< Allow write operation on particular memory region.
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NRF_SPU_MEM_PERM_READ = SPU_FLASHREGION_PERM_READ_Msk ///< Allow read operation from particular memory region.
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} nrf_spu_mem_perm_t;
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/**
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* @brief Function for clearing a specific SPU event.
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*
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* @param[in] p_reg Pointer to the structure of registers of the peripheral.
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* @param[in] event Event to clear.
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*/
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__STATIC_INLINE void nrf_spu_event_clear(NRF_SPU_Type * p_reg,
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nrf_spu_event_t event);
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/**
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* @brief Function for retrieving the state of the SPU event.
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*
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* @param[in] p_reg Pointer to the structure of registers of the peripheral.
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* @param[in] event Event to be checked.
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*
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* @retval true The event has been generated.
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* @retval false The event has not been generated.
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*/
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__STATIC_INLINE bool nrf_spu_event_check(NRF_SPU_Type const * p_reg,
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nrf_spu_event_t event);
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/**
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* @brief Function for enabling specified interrupts.
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*
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* @param[in] p_reg Pointer to the structure of registers of the peripheral.
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* @param[in] mask Interrupts to be enabled.
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*/
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__STATIC_INLINE void nrf_spu_int_enable(NRF_SPU_Type * p_reg,
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uint32_t mask);
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/**
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* @brief Function for disabling specified interrupts.
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*
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* @param[in] p_reg Pointer to the structure of registers of the peripheral.
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* @param[in] mask Interrupts to be disabled.
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*/
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__STATIC_INLINE void nrf_spu_int_disable(NRF_SPU_Type * p_reg,
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uint32_t mask);
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/**
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* @brief Function for retrieving the state of a given interrupt.
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*
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* @param[in] p_reg Pointer to the structure of registers of the peripheral.
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* @param[in] spu_int Interrupt to be checked.
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*
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* @retval true The interrupt is enabled.
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* @retval false The interrupt is not enabled.
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*/
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__STATIC_INLINE bool nrf_spu_int_enable_check(NRF_SPU_Type const * p_reg,
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uint32_t spu_int);
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/**
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* @brief Function for setting up publication configuration of a given SPU event.
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*
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* @param[in] p_reg Pointer to the structure of registers of the peripheral.
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* @param[in] event Event to configure.
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* @param[in] channel Channel to connect with published event.
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*/
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__STATIC_INLINE void nrf_spu_publish_set(NRF_SPU_Type * p_reg,
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nrf_spu_event_t event,
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uint32_t channel);
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/**
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* @brief Function for clearing publication configuration of a given SPU event.
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*
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* @param[in] p_reg Pointer to the structure of registers of the peripheral.
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* @param[in] event Event to clear.
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*/
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__STATIC_INLINE void nrf_spu_publish_clear(NRF_SPU_Type * p_reg,
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nrf_spu_event_t event);
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/**
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* @brief Function for retrieving the capabilities of the current device.
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*
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* @param[in] p_reg Pointer to the structure of registers of the peripheral.
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*
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* @retval true ARM TrustZone support is available.
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* @retval false ARM TrustZone support is not available.
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*/
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__STATIC_INLINE bool nrf_spu_tz_is_available(NRF_SPU_Type const * p_reg);
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/**
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* @brief Function for configuring the DPPI channels to be available in particular domains.
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*
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* Channels are configured as bitmask. Set one in bitmask to make channels available only in secure
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* domain. Set zero to make it available in secure and non-secure domains.
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*
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* @param[in] p_reg Pointer to the structure of registers of the peripheral.
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* @param[in] dppi_id DPPI peripheral id.
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* @param[in] channels_mask Bitmask with channels configuration.
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* @param[in] lock_conf Lock configuration until next SoC reset.
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*/
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__STATIC_INLINE void nrf_spu_dppi_config_set(NRF_SPU_Type * p_reg,
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uint8_t dppi_id,
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uint32_t channels_mask,
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bool lock_conf);
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/**
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* @brief Function for configuring the GPIO pins to be available in particular domains.
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*
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* GPIO pins are configured as bitmask. Set one in bitmask to make particular pin available only
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* in secure domain. Set zero to make it available in secure and non-secure domains.
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*
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* @param[in] p_reg Pointer to the structure of registers of the peripheral.
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* @param[in] gpio_port Port number.
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* @param[in] gpio_mask Bitmask with gpio configuration.
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* @param[in] lock_conf Lock configuration until next SoC reset.
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*/
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__STATIC_INLINE void nrf_spu_gpio_config_set(NRF_SPU_Type * p_reg,
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uint8_t gpio_port,
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uint32_t gpio_mask,
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bool lock_conf);
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/**
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* @brief Function for configuring non-secure callable flash region.
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*
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* @param[in] p_reg Pointer to the structure of registers of the peripheral.
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* @param[in] flash_nsc_id Non-secure callable flash region ID.
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* @param[in] flash_nsc_size Non-secure callable flash region size.
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* @param[in] region_number Flash region number.
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* @param[in] lock_conf Lock configuration until next SoC reset.
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*/
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__STATIC_INLINE void nrf_spu_flashnsc_set(NRF_SPU_Type * p_reg,
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uint8_t flash_nsc_id,
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nrf_spu_nsc_size_t flash_nsc_size,
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uint8_t region_number,
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bool lock_conf);
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/**
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* @brief Function for configuring non-secure callable RAM region.
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*
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* @param[in] p_reg Pointer to the structure of registers of the peripheral.
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* @param[in] ram_nsc_id Non-secure callable RAM region ID.
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* @param[in] ram_nsc_size Non-secure callable RAM region size.
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* @param[in] region_number RAM region number.
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* @param[in] lock_conf Lock configuration until next SoC reset.
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*/
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__STATIC_INLINE void nrf_spu_ramnsc_set(NRF_SPU_Type * p_reg,
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uint8_t ram_nsc_id,
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nrf_spu_nsc_size_t ram_nsc_size,
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uint8_t region_number,
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bool lock_conf);
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/**
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* @brief Function for configuring security for a particular flash region.
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*
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* Permissions parameter must be set by using the logical OR on the @ref nrf_spu_mem_perm_t values.
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*
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* @param[in] p_reg Pointer to the structure of registers of the peripheral.
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* @param[in] region_id Flash region index.
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* @param[in] secure_attr Set region attribute to secure.
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* @param[in] permissions Flash region permissions.
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* @param[in] lock_conf Lock configuration until next SoC reset.
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*/
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__STATIC_INLINE void nrf_spu_flashregion_set(NRF_SPU_Type * p_reg,
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uint8_t region_id,
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bool secure_attr,
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uint32_t permissions,
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bool lock_conf);
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/**
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* @brief Function for configuring security for the RAM region.
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*
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* Permissions parameter must be set by using the logical OR on the @ref nrf_spu_mem_perm_t values.
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*
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* @param[in] p_reg Pointer to the structure of registers of the peripheral.
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* @param[in] region_id RAM region index.
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* @param[in] secure_attr Set region attribute to secure.
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* @param[in] permissions RAM region permissions.
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* @param[in] lock_conf Lock configuration until next SoC reset.
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*/
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__STATIC_INLINE void nrf_spu_ramregion_set(NRF_SPU_Type * p_reg,
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uint8_t region_id,
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bool secure_attr,
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uint32_t permissions,
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bool lock_conf);
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/**
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* @brief Function for configuring access permissions of the peripheral.
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*
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* @param[in] p_reg Pointer to the structure of registers of the peripheral.
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* @param[in] peripheral_id ID number of a particular peripheral.
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* @param[in] secure_attr Peripheral registers accessible only from secure domain.
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* @param[in] secure_dma DMA transfers possible only from RAM memory in secure domain.
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* @param[in] lock_conf Lock configuration until next SoC reset.
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*/
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__STATIC_INLINE void nrf_spu_peripheral_set(NRF_SPU_Type * p_reg,
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uint32_t peripheral_id,
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bool secure_attr,
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bool secure_dma,
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bool lock_conf);
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#ifndef SUPPRESS_INLINE_IMPLEMENTATION
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__STATIC_INLINE void nrf_spu_event_clear(NRF_SPU_Type * p_reg,
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nrf_spu_event_t event)
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{
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*((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
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volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event));
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(void)dummy;
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}
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__STATIC_INLINE bool nrf_spu_event_check(NRF_SPU_Type const * p_reg,
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nrf_spu_event_t event)
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{
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return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
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}
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__STATIC_INLINE void nrf_spu_int_enable(NRF_SPU_Type * p_reg,
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uint32_t mask)
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{
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p_reg->INTENSET = mask;
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}
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__STATIC_INLINE void nrf_spu_int_disable(NRF_SPU_Type * p_reg,
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uint32_t mask)
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{
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p_reg->INTENCLR = mask;
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}
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__STATIC_INLINE bool nrf_spu_int_enable_check(NRF_SPU_Type const * p_reg,
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uint32_t spu_int)
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{
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return (bool)(p_reg->INTENSET & spu_int);
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}
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__STATIC_INLINE void nrf_spu_publish_set(NRF_SPU_Type * p_reg,
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nrf_spu_event_t event,
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uint32_t channel)
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{
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*((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) event + 0x80uL)) =
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(channel | (SPU_PUBLISH_RAMACCERR_EN_Msk));
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}
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__STATIC_INLINE void nrf_spu_publish_clear(NRF_SPU_Type * p_reg,
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nrf_spu_event_t event)
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{
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*((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) event + 0x80uL)) = 0;
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}
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__STATIC_INLINE bool nrf_spu_tz_is_available(NRF_SPU_Type const * p_reg)
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{
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return (p_reg->CAP & SPU_CAP_TZM_Msk ? true : false);
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}
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__STATIC_INLINE void nrf_spu_dppi_config_set(NRF_SPU_Type * p_reg,
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uint8_t dppi_id,
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uint32_t channels_mask,
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bool lock_conf)
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{
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NRFX_ASSERT(!(p_reg->DPPI[dppi_id].LOCK & SPU_DPPI_LOCK_LOCK_Msk));
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p_reg->DPPI[dppi_id].PERM = channels_mask;
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if (lock_conf)
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{
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p_reg->DPPI[dppi_id].LOCK = (SPU_DPPI_LOCK_LOCK_Msk);
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}
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}
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__STATIC_INLINE void nrf_spu_gpio_config_set(NRF_SPU_Type * p_reg,
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uint8_t gpio_port,
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uint32_t gpio_mask,
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bool lock_conf)
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{
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NRFX_ASSERT(!(p_reg->GPIOPORT[gpio_port].LOCK & SPU_GPIOPORT_LOCK_LOCK_Msk));
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p_reg->GPIOPORT[gpio_port].PERM = gpio_mask;
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if (lock_conf)
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{
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p_reg->GPIOPORT[gpio_port].LOCK = (SPU_GPIOPORT_LOCK_LOCK_Msk);
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}
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}
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__STATIC_INLINE void nrf_spu_flashnsc_set(NRF_SPU_Type * p_reg,
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uint8_t flash_nsc_id,
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nrf_spu_nsc_size_t flash_nsc_size,
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uint8_t region_number,
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bool lock_conf)
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{
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NRFX_ASSERT(!(p_reg->FLASHNSC[flash_nsc_id].REGION & SPU_FLASHNSC_REGION_LOCK_Msk));
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NRFX_ASSERT(!(p_reg->FLASHNSC[flash_nsc_id].SIZE & SPU_FLASHNSC_SIZE_LOCK_Msk));
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p_reg->FLASHNSC[flash_nsc_id].REGION = (uint32_t)region_number |
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(lock_conf ? SPU_FLASHNSC_REGION_LOCK_Msk : 0);
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p_reg->FLASHNSC[flash_nsc_id].SIZE = (uint32_t)flash_nsc_size |
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(lock_conf ? SPU_FLASHNSC_SIZE_LOCK_Msk : 0);
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}
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__STATIC_INLINE void nrf_spu_ramnsc_set(NRF_SPU_Type * p_reg,
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uint8_t ram_nsc_id,
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nrf_spu_nsc_size_t ram_nsc_size,
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uint8_t region_number,
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bool lock_conf)
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{
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NRFX_ASSERT(!(p_reg->RAMNSC[ram_nsc_id].REGION & SPU_RAMNSC_REGION_LOCK_Msk));
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NRFX_ASSERT(!(p_reg->RAMNSC[ram_nsc_id].SIZE & SPU_RAMNSC_SIZE_LOCK_Msk));
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p_reg->RAMNSC[ram_nsc_id].REGION = (uint32_t)region_number |
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(lock_conf ? SPU_RAMNSC_REGION_LOCK_Msk : 0);
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p_reg->RAMNSC[ram_nsc_id].SIZE = (uint32_t)ram_nsc_size |
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(lock_conf ? SPU_RAMNSC_SIZE_LOCK_Msk : 0);
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}
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__STATIC_INLINE void nrf_spu_flashregion_set(NRF_SPU_Type * p_reg,
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uint8_t region_id,
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bool secure_attr,
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uint32_t permissions,
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bool lock_conf)
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{
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NRFX_ASSERT(!(p_reg->FLASHREGION[region_id].PERM & SPU_FLASHREGION_PERM_LOCK_Msk));
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p_reg->FLASHREGION[region_id].PERM = permissions |
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(secure_attr ? SPU_FLASHREGION_PERM_SECATTR_Msk : 0) |
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(lock_conf ? SPU_FLASHREGION_PERM_LOCK_Msk : 0);
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}
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__STATIC_INLINE void nrf_spu_ramregion_set(NRF_SPU_Type * p_reg,
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uint8_t region_id,
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bool secure_attr,
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uint32_t permissions,
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bool lock_conf)
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{
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NRFX_ASSERT(!(p_reg->RAMREGION[region_id].PERM & SPU_RAMREGION_PERM_LOCK_Msk));
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p_reg->RAMREGION[region_id].PERM = permissions |
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(secure_attr ? SPU_RAMREGION_PERM_SECATTR_Msk : 0) |
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(lock_conf ? SPU_RAMREGION_PERM_LOCK_Msk : 0);
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}
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__STATIC_INLINE void nrf_spu_peripheral_set(NRF_SPU_Type * p_reg,
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uint32_t peripheral_id,
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bool secure_attr,
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bool secure_dma,
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bool lock_conf)
|
|
{
|
|
NRFX_ASSERT(p_reg->PERIPHID[peripheral_id].PERM & SPU_PERIPHID_PERM_PRESENT_Msk);
|
|
NRFX_ASSERT(!(p_reg->PERIPHID[peripheral_id].PERM & SPU_PERIPHID_PERM_LOCK_Msk));
|
|
|
|
p_reg->PERIPHID[peripheral_id].PERM =
|
|
(secure_attr ? SPU_PERIPHID_PERM_SECATTR_Msk : 0) |
|
|
(secure_dma ? SPU_PERIPHID_PERM_DMASEC_Msk : 0) |
|
|
(lock_conf ? SPU_PERIPHID_PERM_LOCK_Msk : 0);
|
|
}
|
|
|
|
#endif // SUPPRESS_INLINE_IMPLEMENTATION
|
|
|
|
/** @} */
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
|
#endif // NRF_SPU_H__
|
|
|