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369 lines
10 KiB
369 lines
10 KiB
/**
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* \file
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*
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* \brief SAM TC
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*
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* Copyright (C) 2015 - 2017 Atmel Corporation. All rights reserved.
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*
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* \asf_license_start
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*
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* \page License
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. The name of Atmel may not be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* 4. This software may only be redistributed and used in connection with an
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* Atmel microcontroller product.
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*
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* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* \asf_license_stop
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*
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*/
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#include <hpl_pwm.h>
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#include <hpl_tc_config.h>
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#include <hpl_timer.h>
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#include <utils.h>
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#include <utils_assert.h>
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#include <hpl_tc_base.h>
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#ifndef CONF_TC3_ENABLE
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#define CONF_TC3_ENABLE 0
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#endif
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#ifndef CONF_TC4_ENABLE
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#define CONF_TC4_ENABLE 0
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#endif
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#ifndef CONF_TC5_ENABLE
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#define CONF_TC5_ENABLE 0
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#endif
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#ifndef CONF_TC6_ENABLE
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#define CONF_TC6_ENABLE 0
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#endif
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#ifndef CONF_TC7_ENABLE
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#define CONF_TC7_ENABLE 0
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#endif
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/**
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* \brief TC IRQ base index
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*/
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#define TC_IRQ_BASE_INDEX ((uint8_t)TC3_IRQn)
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/**
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* \brief TC base address
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*/
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#define TC_HW_BASE_ADDR ((uint32_t)TC3)
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/**
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* \brief TC number offset
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*/
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#define TC_NUMBER_OFFSET 3
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/**
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* \brief Macro is used to fill usart configuration structure based on its
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* number
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*
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* \param[in] n The number of structures
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*/
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#define TC_CONFIGURATION(n) \
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{ \
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(n), TC_CTRLA_MODE(CONF_TC##n##_MODE) | TC_CTRLA_WAVEGEN(TC_CTRLA_WAVEGEN_MPWM_Val) \
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| TC_CTRLA_PRESCALER(CONF_TC##n##_PRESCALER) | (CONF_TC##n##_RUNSTDBY << TC_CTRLA_RUNSTDBY_Pos) \
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| TC_CTRLA_PRESCSYNC(CONF_TC##n##_PRESCSYNC), \
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(CONF_TC##n##_DBGRUN << TC_DBGCTRL_DBGRUN_Pos), \
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(CONF_TC##n##_OVFEO << TC_EVCTRL_OVFEO_Pos) | (CONF_TC##n##_TCEI << TC_EVCTRL_TCEI_Pos) \
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| (CONF_TC##n##_TCINV << TC_EVCTRL_TCINV_Pos) | (CONF_TC##n##_EVACT << TC_EVCTRL_EVACT_Pos) \
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| (CONF_TC##n##_MCEO0 << TC_EVCTRL_MCEO0_Pos) | (CONF_TC##n##_MCEO1 << TC_EVCTRL_MCEO1_Pos), \
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CONF_TC##n##_PER, CONF_TC##n##_CC0, CONF_TC##n##_CC1 \
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}
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/**
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* \brief TC configuration type
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*/
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struct tc_configuration {
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uint8_t number;
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hri_tc_ctrla_reg_t ctrl_a;
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hri_tc_dbgctrl_reg_t dbg_ctrl;
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hri_tc_evctrl_reg_t event_ctrl;
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hri_tc_per_reg_t per;
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hri_tc_cc32_reg_t cc0;
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hri_tc_cc32_reg_t cc1;
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};
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/**
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* \brief Array of TC configurations
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*/
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static struct tc_configuration _tcs[] = {
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#if CONF_TC3_ENABLE == 1
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TC_CONFIGURATION(3),
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#endif
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#if CONF_TC4_ENABLE == 1
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TC_CONFIGURATION(4),
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#endif
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#if CONF_TC5_ENABLE == 1
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TC_CONFIGURATION(5),
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#endif
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#if CONF_TC6_ENABLE == 1
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TC_CONFIGURATION(6),
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#endif
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#if CONF_TC7_ENABLE == 1
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TC_CONFIGURATION(7),
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#endif
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};
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static struct _pwm_device *_tc3_dev = NULL;
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static int8_t get_tc_index(const void *const hw);
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static uint8_t tc_get_hardware_index(const void *const hw);
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static void _tc_init_irq_param(const void *const hw, void *dev);
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static inline uint8_t _get_hardware_offset(const void *const hw);
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/**
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* \brief Initialize TC for PWM mode
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*/
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int32_t _pwm_init(struct _pwm_device *const device, void *const hw)
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{
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int8_t i = get_tc_index(hw);
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device->hw = hw;
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hri_tc_wait_for_sync(hw);
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if (hri_tc_get_CTRLA_ENABLE_bit(hw)) {
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return ERR_DENIED;
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}
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hri_tc_set_CTRLA_SWRST_bit(hw);
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hri_tc_wait_for_sync(hw);
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hri_tc_write_CTRLA_reg(hw, _tcs[i].ctrl_a);
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hri_tc_write_DBGCTRL_reg(hw, _tcs[i].dbg_ctrl);
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hri_tc_write_EVCTRL_reg(hw, _tcs[i].event_ctrl);
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if ((_tcs[i].ctrl_a & TC_CTRLA_MODE_Msk) == TC_CTRLA_MODE_COUNT32) {
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hri_tccount32_write_CC_reg(hw, 0, _tcs[i].cc0);
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hri_tccount32_write_CC_reg(hw, 1, _tcs[i].cc1);
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} else if ((_tcs[i].ctrl_a & TC_CTRLA_MODE_Msk) == TC_CTRLA_MODE_COUNT16) {
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hri_tccount16_write_CC_reg(hw, 0, (hri_tc_count16_reg_t)_tcs[i].cc0);
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hri_tccount16_write_CC_reg(hw, 1, (hri_tc_count16_reg_t)_tcs[i].cc1);
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} else {
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/* 8-bit resolution is not accepted by duty cycle control */
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return ERR_INVALID_DATA;
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}
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_tc_init_irq_param(hw, (void *)device);
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NVIC_DisableIRQ((IRQn_Type)((uint8_t)TC_IRQ_BASE_INDEX + tc_get_hardware_index(hw)));
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NVIC_ClearPendingIRQ((IRQn_Type)((uint8_t)TC_IRQ_BASE_INDEX + tc_get_hardware_index(hw)));
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NVIC_EnableIRQ((IRQn_Type)((uint8_t)TC_IRQ_BASE_INDEX + tc_get_hardware_index(hw)));
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return ERR_NONE;
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}
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/**
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* \brief De-initialize TC for PWM mode
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*/
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void _pwm_deinit(struct _pwm_device *const device)
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{
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void *const hw = device->hw;
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NVIC_DisableIRQ((IRQn_Type)(TC_IRQ_BASE_INDEX + tc_get_hardware_index(hw)));
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hri_tc_clear_CTRLA_ENABLE_bit(hw);
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hri_tc_set_CTRLA_SWRST_bit(hw);
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}
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/**
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* \brief Start PWM
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*/
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void _pwm_enable(struct _pwm_device *const device)
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{
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hri_tc_set_CTRLA_ENABLE_bit(device->hw);
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}
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/**
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* \brief Stop PWM
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*/
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void _pwm_disable(struct _pwm_device *const device)
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{
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hri_tc_clear_CTRLA_ENABLE_bit(device->hw);
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}
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/**
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* \brief Set PWM parameter
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*/
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void _pwm_set_param(struct _pwm_device *const device, const pwm_period_t period, const pwm_period_t duty_cycle)
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{
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int8_t i = get_tc_index(device->hw);
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void *const hw = device->hw;
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_tcs[i].cc0 = period;
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_tcs[i].cc1 = duty_cycle;
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if ((_tcs[i].ctrl_a & TC_CTRLA_MODE_Msk) == TC_CTRLA_MODE_COUNT32) {
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hri_tccount32_write_CC_reg(hw, 0, _tcs[i].cc0);
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hri_tccount32_write_CC_reg(hw, 1, _tcs[i].cc1);
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} else {
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hri_tccount16_write_CC_reg(hw, 0, _tcs[i].cc0);
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hri_tccount16_write_CC_reg(hw, 1, _tcs[i].cc1);
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}
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}
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/**
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* \brief Get pwm waveform period value
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*/
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pwm_period_t _pwm_get_period(const struct _pwm_device *const device)
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{
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void *const hw = device->hw;
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int8_t i = get_tc_index(hw);
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if ((_tcs[i].ctrl_a & TC_CTRLA_MODE_Msk) == TC_CTRLA_MODE_COUNT32) {
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return (pwm_period_t)(hri_tccount32_read_CC_reg(hw, 0));
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} else {
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return (pwm_period_t)(hri_tccount16_read_CC_reg(hw, 0));
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}
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}
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/**
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* \brief Get pwm waveform duty cycle
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*/
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uint32_t _pwm_get_duty(const struct _pwm_device *const device)
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{
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void *const hw = device->hw;
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int8_t i = get_tc_index(hw);
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uint32_t per;
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uint32_t duty_cycle;
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if ((_tcs[i].ctrl_a & TC_CTRLA_MODE_Msk) == TC_CTRLA_MODE_COUNT32) {
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per = hri_tccount32_read_CC_reg(hw, 0);
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duty_cycle = hri_tccount32_read_CC_reg(hw, 1);
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} else {
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per = hri_tccount16_read_CC_reg(hw, 0);
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duty_cycle = hri_tccount16_read_CC_reg(hw, 1);
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}
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return ((duty_cycle * 1000) / per);
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}
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/**
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* \brief Check if PWM is running
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*/
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bool _pwm_is_enabled(const struct _pwm_device *const device)
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{
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return hri_tc_get_CTRLA_ENABLE_bit(device->hw);
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}
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/**
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* \brief Enable/disable PWM interrupt
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*/
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void _pwm_set_irq_state(struct _pwm_device *const device, const enum _pwm_callback_type type, const bool disable)
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{
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ASSERT(device);
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if (PWM_DEVICE_PERIOD_CB == type) {
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hri_tc_write_INTEN_OVF_bit(device->hw, disable);
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} else if (PWM_DEVICE_ERROR_CB == type) {
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hri_tc_write_INTEN_ERR_bit(device->hw, disable);
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}
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}
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/**
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* \brief Retrieve timer helper functions
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*/
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struct _timer_hpl_interface *_tc_get_timer(void)
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{
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return NULL;
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}
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/**
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* \brief Retrieve pwm helper functions
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*/
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struct _pwm_hpl_interface *_tc_get_pwm(void)
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{
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return NULL;
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}
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/**
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* \internal TC interrupt handler for PWM
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*
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* \param[in] instance TC instance number
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*/
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static void tc_pwm_interrupt_handler(struct _pwm_device *device)
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{
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void *const hw = device->hw;
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if (hri_tc_get_interrupt_OVF_bit(hw)) {
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hri_tc_clear_interrupt_OVF_bit(hw);
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if (NULL != device->callback.pwm_period_cb) {
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device->callback.pwm_period_cb(device);
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}
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}
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if (hri_tc_get_INTEN_ERR_bit(hw)) {
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hri_tc_clear_interrupt_ERR_bit(hw);
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if (NULL != device->callback.pwm_error_cb) {
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device->callback.pwm_error_cb(device);
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}
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}
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}
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/**
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* \brief TC interrupt handler
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*/
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void TC3_Handler(void)
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{
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tc_pwm_interrupt_handler(_tc3_dev);
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}
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/**
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* \internal Retrieve TC hardware index
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*
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* \param[in] hw The pointer to hardware instance
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*/
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static uint8_t tc_get_hardware_index(const void *const hw)
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{
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#ifndef _UNIT_TEST_
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return ((uint32_t)hw - TC_HW_BASE_ADDR) >> 10;
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#else
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return ((uint32_t)hw - TC_HW_BASE_ADDR) / sizeof(Tc);
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#endif
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}
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/**
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* \internal Retrieve TC index
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*
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* \param[in] hw The pointer to hardware instance
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*
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* \return The index of TC configuration
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*/
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static int8_t get_tc_index(const void *const hw)
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{
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uint8_t tc_offset = tc_get_hardware_index(hw) + TC_NUMBER_OFFSET;
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uint8_t i;
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for (i = 0; i < ARRAY_SIZE(_tcs); i++) {
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if (_tcs[i].number == tc_offset) {
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return i;
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}
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}
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ASSERT(false);
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return -1;
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}
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/**
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* \brief Init irq param with the given tc hardware instance
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*/
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static void _tc_init_irq_param(const void *const hw, void *dev)
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{
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if (hw == TC3) {
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_tc3_dev = (struct _pwm_device *)dev;
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}
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}
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static inline uint8_t _get_hardware_offset(const void *const hw)
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{
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return (((uint32_t)hw - TC_HW_BASE_ADDR) >> 10) + TC_NUMBER_OFFSET;
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}
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