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761 lines
21 KiB
761 lines
21 KiB
/**
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* \file
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*
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* \brief SAM Analog Digital Converter
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*
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* Copyright (C) 2015-2017 Atmel Corporation. All rights reserved.
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*
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* \asf_license_start
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*
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* \page License
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. The name of Atmel may not be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* 4. This software may only be redistributed and used in connection with an
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* Atmel microcontroller product.
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*
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* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* \asf_license_stop
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*
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*/
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#include <hpl_adc_async.h>
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#include <hpl_adc_dma.h>
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#include <hpl_adc_sync.h>
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#include <utils_assert.h>
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#include <utils_repeat_macro.h>
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#include <hpl_adc_config.h>
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#define ADC_CONFIGURATION(n) \
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{ \
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(n), (CONF_ADC_##n##_RUNSTDBY << ADC_CTRLA_RUNSTDBY_Pos) | (CONF_ADC_##n##_ENABLE << ADC_CTRLA_ENABLE_Pos), \
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(CONF_ADC_##n##_REFCOMP << ADC_REFCTRL_REFCOMP_Pos) | ADC_REFCTRL_REFSEL(CONF_ADC_##n##_REFSEL), \
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ADC_AVGCTRL_ADJRES(CONF_ADC_##n##_ADJRES) | ADC_AVGCTRL_SAMPLENUM(CONF_ADC_##n##_SAMPLENUM), \
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ADC_SAMPCTRL_SAMPLEN(CONF_ADC_##n##_SAMPLEN), \
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ADC_CTRLB_PRESCALER(CONF_ADC_##n##_PRESCALER) | (CONF_ADC_##n##_RESSEL << ADC_CTRLB_RESSEL_Pos) \
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| (CONF_ADC_##n##_CORREN << ADC_CTRLB_CORREN_Pos) | (CONF_ADC_##n##_FREERUN << ADC_CTRLB_FREERUN_Pos) \
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| (CONF_ADC_##n##_LEFTADJ << ADC_CTRLB_LEFTADJ_Pos) \
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| (CONF_ADC_##n##_DIFFMODE << ADC_CTRLB_DIFFMODE_Pos), \
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CONF_ADC_##n##_WINMODE, \
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ADC_INPUTCTRL_GAIN(CONF_ADC_##n##_GAIN) | ADC_INPUTCTRL_INPUTOFFSET(CONF_ADC_##n##_INPUTOFFSET) \
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| ADC_INPUTCTRL_INPUTSCAN(CONF_ADC_##n##_INPUTSCAN) \
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| (CONF_ADC_##n##_MUXNEG << ADC_INPUTCTRL_MUXNEG_Pos) \
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| (CONF_ADC_##n##_MUXPOS << ADC_INPUTCTRL_MUXPOS_Pos), \
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(CONF_ADC_##n##_WINMONEO << ADC_EVCTRL_WINMONEO_Pos) \
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| (CONF_ADC_##n##_RESRDYEO << ADC_EVCTRL_RESRDYEO_Pos) \
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| (CONF_ADC_##n##_SYNCEI << ADC_EVCTRL_SYNCEI_Pos) \
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| (CONF_ADC_##n##_STARTEI << ADC_EVCTRL_STARTEI_Pos), \
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CONF_ADC_##n##_WINLT, CONF_ADC_##n##_WINUT, ADC_GAINCORR_GAINCORR(CONF_ADC_##n##_GAINCORR), \
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ADC_OFFSETCORR_OFFSETCORR(CONF_ADC_##n##_OFFSETCORR), (CONF_ADC_##n##_DBGRUN << ADC_DBGCTRL_DBGRUN_Pos), \
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}
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/**
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* \brief ADC configuration type
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*/
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struct adc_configuration {
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uint8_t number;
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hri_adc_ctrla_reg_t ctrl_a;
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hri_adc_refctrl_reg_t ref_ctrl;
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hri_adc_avgctrl_reg_t avg_ctrl;
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hri_adc_sampctrl_reg_t samp_ctrl;
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hri_adc_ctrlb_reg_t ctrl_b;
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hri_adc_winctrl_reg_t win_ctrl;
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hri_adc_inputctrl_reg_t input_ctrl;
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hri_adc_evctrl_reg_t ev_ctrl;
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hri_adc_winlt_reg_t win_lt;
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hri_adc_winut_reg_t win_ut;
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hri_adc_gaincorr_reg_t gain_corr;
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hri_adc_offsetcorr_reg_t offset_corr;
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hri_adc_dbgctrl_reg_t dbg_ctrl;
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};
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#define ADC_AMOUNT (CONF_ADC_0_ENABLE)
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/**
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* \brief Array of ADC configurations
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*/
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static struct adc_configuration _adcs[] = {
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#if CONF_ADC_0_ENABLE == 1
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ADC_CONFIGURATION(0),
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#endif
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};
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/*!< Pointer to hpl device */
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static struct _adc_async_device *_adc_dev = NULL;
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static void _adc_set_resolution(void *const hw, const adc_resolution_t resolution);
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static void _adc_set_conversion_mode(void *const hw, const enum adc_conversion_mode mode);
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static void _adc_set_channel_differential_mode(void *const hw, const uint8_t channel,
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const enum adc_differential_mode mode);
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/**
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* \brief Retrieve ordinal number of the given adc hardware instance
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*/
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static uint8_t _adc_get_hardware_index(const void *const hw)
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{
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(void)hw;
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return 0;
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}
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/** \brief Return the pointer to register settings of specific ADC
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* \param[in] hw_addr The hardware register base address.
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* \return Pointer to register settings of specific ADC.
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*/
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static uint8_t _adc_get_regs(const uint32_t hw_addr)
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{
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uint8_t n = _adc_get_hardware_index((const void *)hw_addr);
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uint8_t i;
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for (i = 0; i < sizeof(_adcs) / sizeof(struct adc_configuration); i++) {
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if (_adcs[i].number == n) {
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return i;
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}
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}
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ASSERT(false);
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return 0;
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}
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/**
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* \brief Retrieve IRQ number for the given hardware instance
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*/
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static uint8_t _adc_get_irq_num(const struct _adc_async_device *const device)
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{
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(void)device;
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return ADC_IRQn;
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}
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/**
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* \brief Initialize ADC
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*
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* \param[in] hw The pointer to hardware instance
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* \param[in] i The number of hardware instance
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*/
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static int32_t _adc_init(void *const hw, const uint8_t i)
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{
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ASSERT(hw == ADC);
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hri_adc_wait_for_sync(hw);
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if (hri_adc_get_CTRLA_ENABLE_bit(hw)) {
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return ERR_DENIED;
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}
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hri_adc_set_CTRLA_SWRST_bit(hw);
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hri_adc_wait_for_sync(hw);
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hri_adc_write_REFCTRL_reg(hw, _adcs[i].ref_ctrl);
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hri_adc_write_AVGCTRL_reg(hw, _adcs[i].avg_ctrl);
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hri_adc_write_SAMPCTRL_reg(hw, _adcs[i].samp_ctrl);
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hri_adc_write_EVCTRL_reg(hw, _adcs[i].ev_ctrl);
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hri_adc_write_GAINCORR_reg(hw, _adcs[i].gain_corr);
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hri_adc_write_OFFSETCORR_reg(hw, _adcs[i].offset_corr);
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hri_adc_write_DBGCTRL_reg(hw, _adcs[i].dbg_ctrl);
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hri_adc_write_CTRLB_reg(hw, _adcs[i].ctrl_b);
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hri_adc_write_INPUTCTRL_reg(hw, _adcs[i].input_ctrl);
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hri_adc_write_WINCTRL_reg(hw, _adcs[i].win_ctrl);
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hri_adc_write_WINLT_reg(hw, _adcs[i].win_lt);
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hri_adc_write_WINUT_reg(hw, _adcs[i].win_ut);
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hri_adc_write_CTRLA_reg(hw, _adcs[i].ctrl_a);
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return ERR_NONE;
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}
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/**
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* \brief De-initialize ADC
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*
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* \param[in] hw The pointer to hardware instance
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*/
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static inline void _adc_deinit(void *const hw)
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{
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hri_adc_clear_CTRLA_ENABLE_bit(hw);
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hri_adc_set_CTRLA_SWRST_bit(hw);
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}
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/**
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* \brief Initialize ADC
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*/
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int32_t _adc_sync_init(struct _adc_sync_device *const device, void *const hw)
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{
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ASSERT(device);
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device->hw = hw;
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return _adc_init(hw, _adc_get_regs((uint32_t)hw));
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}
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/**
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* \brief Initialize ADC
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*/
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int32_t _adc_async_init(struct _adc_async_device *const device, void *const hw)
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{
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int32_t init_status;
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ASSERT(device);
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init_status = _adc_init(hw, _adc_get_regs((uint32_t)hw));
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if (init_status) {
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return init_status;
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}
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device->hw = hw;
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_adc_dev = device;
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NVIC_DisableIRQ(ADC_IRQn);
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NVIC_ClearPendingIRQ(ADC_IRQn);
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NVIC_EnableIRQ(ADC_IRQn);
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return ERR_NONE;
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}
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/**
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* \brief Initialize ADC
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*/
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int32_t _adc_dma_init(struct _adc_dma_device *const device, void *const hw)
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{
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ASSERT(device);
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device->hw = hw;
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return _adc_init(hw, _adc_get_regs((uint32_t)hw));
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}
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/**
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* \brief De-initialize ADC
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*/
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void _adc_sync_deinit(struct _adc_sync_device *const device)
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{
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_adc_deinit(device->hw);
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}
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/**
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* \brief De-initialize ADC
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*/
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void _adc_async_deinit(struct _adc_async_device *const device)
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{
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NVIC_DisableIRQ(_adc_get_irq_num(device));
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NVIC_ClearPendingIRQ(_adc_get_irq_num(device));
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_adc_deinit(device->hw);
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}
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/**
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* \brief De-initialize ADC
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*/
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void _adc_dma_deinit(struct _adc_dma_device *const device)
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{
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_adc_deinit(device->hw);
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}
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/**
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* \brief Enable ADC
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*/
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void _adc_sync_enable_channel(struct _adc_sync_device *const device, const uint8_t channel)
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{
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(void)channel;
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hri_adc_set_CTRLA_ENABLE_bit(device->hw);
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}
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/**
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* \brief Enable ADC
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*/
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void _adc_async_enable_channel(struct _adc_async_device *const device, const uint8_t channel)
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{
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(void)channel;
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hri_adc_set_CTRLA_ENABLE_bit(device->hw);
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}
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/**
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* \brief Enable ADC
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*/
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void _adc_dma_enable_channel(struct _adc_dma_device *const device, const uint8_t channel)
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{
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(void)channel;
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hri_adc_set_CTRLA_ENABLE_bit(device->hw);
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}
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/**
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* \brief Disable ADC
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*/
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void _adc_sync_disable_channel(struct _adc_sync_device *const device, const uint8_t channel)
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{
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(void)channel;
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hri_adc_clear_CTRLA_ENABLE_bit(device->hw);
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}
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/**
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* \brief Disable ADC
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*/
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void _adc_async_disable_channel(struct _adc_async_device *const device, const uint8_t channel)
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{
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(void)channel;
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hri_adc_clear_CTRLA_ENABLE_bit(device->hw);
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}
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/**
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* \brief Disable ADC
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*/
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void _adc_dma_disable_channel(struct _adc_dma_device *const device, const uint8_t channel)
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{
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(void)channel;
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hri_adc_clear_CTRLA_ENABLE_bit(device->hw);
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}
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/**
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* \brief Return address of ADC DMA source
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*/
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uint32_t _adc_get_source_for_dma(struct _adc_dma_device *const device)
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{
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return (uint32_t) & (((Adc *)(device->hw))->RESULT.reg);
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}
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/**
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* \brief Retrieve ADC conversion data size
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*/
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uint8_t _adc_sync_get_data_size(const struct _adc_sync_device *const device)
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{
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return hri_adc_read_CTRLB_RESSEL_bf(device->hw) == ADC_CTRLB_RESSEL_8BIT_Val ? 1 : 2;
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}
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/**
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* \brief Retrieve ADC conversion data size
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*/
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uint8_t _adc_async_get_data_size(const struct _adc_async_device *const device)
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{
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return hri_adc_read_CTRLB_RESSEL_bf(device->hw) == ADC_CTRLB_RESSEL_8BIT_Val ? 1 : 2;
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}
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/**
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* \brief Retrieve ADC conversion data size
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*/
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uint8_t _adc_dma_get_data_size(const struct _adc_dma_device *const device)
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{
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return hri_adc_read_CTRLB_RESSEL_bf(device->hw) == ADC_CTRLB_RESSEL_8BIT_Val ? 1 : 2;
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}
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/**
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* \brief Check if conversion is done
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*/
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bool _adc_sync_is_channel_conversion_done(const struct _adc_sync_device *const device, const uint8_t channel)
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{
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(void)channel;
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return hri_adc_get_interrupt_RESRDY_bit(device->hw);
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}
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/**
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* \brief Check if conversion is done
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*/
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bool _adc_async_is_channel_conversion_done(const struct _adc_async_device *const device, const uint8_t channel)
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{
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(void)channel;
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return hri_adc_get_interrupt_RESRDY_bit(device->hw);
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}
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/**
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* \brief Check if conversion is done
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*/
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bool _adc_dma_is_conversion_done(const struct _adc_dma_device *const device)
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{
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return hri_adc_get_interrupt_RESRDY_bit(device->hw);
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}
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/**
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* \brief Make conversion
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*/
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void _adc_sync_convert(struct _adc_sync_device *const device)
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{
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hri_adc_set_SWTRIG_START_bit(device->hw);
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}
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/**
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* \brief Make conversion
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*/
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void _adc_async_convert(struct _adc_async_device *const device)
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{
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hri_adc_set_SWTRIG_START_bit(device->hw);
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}
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/**
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* \brief Make conversion
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*/
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void _adc_dma_convert(struct _adc_dma_device *const device)
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{
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hri_adc_set_SWTRIG_START_bit(device->hw);
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}
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/**
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* \brief Retrieve the conversion result
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*/
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uint16_t _adc_sync_read_channel_data(const struct _adc_sync_device *const device, const uint8_t channel)
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{
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(void)channel;
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return hri_adc_read_RESULT_reg(device->hw);
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}
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/**
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* \brief Retrieve the conversion result
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*/
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uint16_t _adc_async_read_channel_data(const struct _adc_async_device *const device, const uint8_t channel)
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{
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(void)channel;
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return hri_adc_read_RESULT_reg(device->hw);
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}
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/**
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* \brief Set reference source
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*/
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void _adc_sync_set_reference_source(struct _adc_sync_device *const device, const adc_reference_t reference)
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{
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hri_adc_write_REFCTRL_REFSEL_bf(device->hw, reference);
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}
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/**
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* \brief Set reference source
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*/
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void _adc_async_set_reference_source(struct _adc_async_device *const device, const adc_reference_t reference)
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{
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hri_adc_write_REFCTRL_REFSEL_bf(device->hw, reference);
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}
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/**
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* \brief Set reference source
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*/
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void _adc_dma_set_reference_source(struct _adc_dma_device *const device, const adc_reference_t reference)
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{
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hri_adc_write_REFCTRL_REFSEL_bf(device->hw, reference);
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}
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/**
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* \brief Set resolution
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*/
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void _adc_sync_set_resolution(struct _adc_sync_device *const device, const adc_resolution_t resolution)
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{
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_adc_set_resolution(device->hw, resolution);
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}
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/**
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* \brief Set resolution
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*/
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void _adc_async_set_resolution(struct _adc_async_device *const device, const adc_resolution_t resolution)
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{
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_adc_set_resolution(device->hw, resolution);
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}
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/**
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* \brief Set resolution
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*/
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void _adc_dma_set_resolution(struct _adc_dma_device *const device, const adc_resolution_t resolution)
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{
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hri_adc_write_CTRLB_RESSEL_bf(device->hw, resolution);
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}
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/**
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* \brief Set channels input sources
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*/
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void _adc_sync_set_inputs(struct _adc_sync_device *const device, const adc_pos_input_t pos_input,
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const adc_neg_input_t neg_input, const uint8_t channel)
|
|
{
|
|
(void)channel;
|
|
|
|
hri_adc_write_INPUTCTRL_MUXPOS_bf(device->hw, pos_input);
|
|
hri_adc_write_INPUTCTRL_MUXNEG_bf(device->hw, neg_input);
|
|
}
|
|
|
|
/**
|
|
* \brief Set channels input sources
|
|
*/
|
|
void _adc_async_set_inputs(struct _adc_async_device *const device, const adc_pos_input_t pos_input,
|
|
const adc_neg_input_t neg_input, const uint8_t channel)
|
|
{
|
|
(void)channel;
|
|
|
|
hri_adc_write_INPUTCTRL_MUXPOS_bf(device->hw, pos_input);
|
|
hri_adc_write_INPUTCTRL_MUXNEG_bf(device->hw, neg_input);
|
|
}
|
|
|
|
/**
|
|
* \brief Set channels input source
|
|
*/
|
|
void _adc_dma_set_inputs(struct _adc_dma_device *const device, const adc_pos_input_t pos_input,
|
|
const adc_neg_input_t neg_input, const uint8_t channel)
|
|
{
|
|
(void)channel;
|
|
|
|
hri_adc_write_INPUTCTRL_MUXPOS_bf(device->hw, pos_input);
|
|
hri_adc_write_INPUTCTRL_MUXNEG_bf(device->hw, neg_input);
|
|
}
|
|
|
|
/**
|
|
* \brief Set thresholds
|
|
*/
|
|
void _adc_sync_set_thresholds(struct _adc_sync_device *const device, const adc_threshold_t low_threshold,
|
|
const adc_threshold_t up_threshold)
|
|
{
|
|
hri_adc_write_WINLT_reg(device->hw, low_threshold);
|
|
hri_adc_write_WINUT_reg(device->hw, up_threshold);
|
|
}
|
|
|
|
/**
|
|
* \brief Set threshold
|
|
*/
|
|
void _adc_async_set_thresholds(struct _adc_async_device *const device, const adc_threshold_t low_threshold,
|
|
const adc_threshold_t up_threshold)
|
|
{
|
|
hri_adc_write_WINLT_reg(device->hw, low_threshold);
|
|
hri_adc_write_WINUT_reg(device->hw, up_threshold);
|
|
}
|
|
|
|
/**
|
|
* \brief Set thresholds
|
|
*/
|
|
void _adc_dma_set_thresholds(struct _adc_dma_device *const device, const adc_threshold_t low_threshold,
|
|
const adc_threshold_t up_threshold)
|
|
{
|
|
hri_adc_write_WINLT_reg(device->hw, low_threshold);
|
|
hri_adc_write_WINUT_reg(device->hw, up_threshold);
|
|
}
|
|
|
|
/**
|
|
* \brief Set gain
|
|
*/
|
|
void _adc_sync_set_channel_gain(struct _adc_sync_device *const device, const uint8_t channel, const adc_gain_t gain)
|
|
{
|
|
(void)channel;
|
|
|
|
hri_adc_write_INPUTCTRL_GAIN_bf(device->hw, gain);
|
|
}
|
|
|
|
/**
|
|
* \brief Set gain
|
|
*/
|
|
void _adc_async_set_channel_gain(struct _adc_async_device *const device, const uint8_t channel, const adc_gain_t gain)
|
|
{
|
|
(void)channel;
|
|
|
|
hri_adc_write_INPUTCTRL_GAIN_bf(device->hw, gain);
|
|
}
|
|
|
|
/**
|
|
* \brief Set gain
|
|
*/
|
|
void _adc_dma_set_channel_gain(struct _adc_dma_device *const device, const uint8_t channel, const adc_gain_t gain)
|
|
{
|
|
(void)channel;
|
|
|
|
hri_adc_write_INPUTCTRL_GAIN_bf(device->hw, gain);
|
|
}
|
|
|
|
/**
|
|
* \brief Set conversion mode
|
|
*/
|
|
void _adc_sync_set_conversion_mode(struct _adc_sync_device *const device, const enum adc_conversion_mode mode)
|
|
{
|
|
_adc_set_conversion_mode(device->hw, mode);
|
|
}
|
|
|
|
/**
|
|
* \brief Set conversion mode
|
|
*/
|
|
void _adc_async_set_conversion_mode(struct _adc_async_device *const device, const enum adc_conversion_mode mode)
|
|
{
|
|
_adc_set_conversion_mode(device->hw, mode);
|
|
}
|
|
|
|
/**
|
|
* \brief Set conversion mode
|
|
*/
|
|
void _adc_dma_set_conversion_mode(struct _adc_dma_device *const device, const enum adc_conversion_mode mode)
|
|
{
|
|
_adc_set_conversion_mode(device->hw, mode);
|
|
}
|
|
|
|
/**
|
|
* \brief Set differential mode
|
|
*/
|
|
void _adc_sync_set_channel_differential_mode(struct _adc_sync_device *const device, const uint8_t channel,
|
|
const enum adc_differential_mode mode)
|
|
{
|
|
_adc_set_channel_differential_mode(device->hw, channel, mode);
|
|
}
|
|
|
|
/**
|
|
* \brief Set differential mode
|
|
*/
|
|
void _adc_async_set_channel_differential_mode(struct _adc_async_device *const device, const uint8_t channel,
|
|
const enum adc_differential_mode mode)
|
|
{
|
|
_adc_set_channel_differential_mode(device->hw, channel, mode);
|
|
}
|
|
|
|
/**
|
|
* \brief Set differential mode
|
|
*/
|
|
void _adc_dma_set_channel_differential_mode(struct _adc_dma_device *const device, const uint8_t channel,
|
|
const enum adc_differential_mode mode)
|
|
{
|
|
(void)channel;
|
|
|
|
_adc_set_channel_differential_mode(device->hw, channel, mode);
|
|
}
|
|
|
|
/**
|
|
* \brief Set window mode
|
|
*/
|
|
void _adc_sync_set_window_mode(struct _adc_sync_device *const device, const adc_window_mode_t mode)
|
|
{
|
|
hri_adc_write_WINCTRL_WINMODE_bf(device->hw, mode);
|
|
}
|
|
|
|
/**
|
|
* \brief Set window mode
|
|
*/
|
|
void _adc_async_set_window_mode(struct _adc_async_device *const device, const adc_window_mode_t mode)
|
|
{
|
|
hri_adc_write_WINCTRL_WINMODE_bf(device->hw, mode);
|
|
}
|
|
|
|
/**
|
|
* \brief Set window mode
|
|
*/
|
|
void _adc_dma_set_window_mode(struct _adc_dma_device *const device, const adc_window_mode_t mode)
|
|
{
|
|
hri_adc_write_WINCTRL_WINMODE_bf(device->hw, mode);
|
|
}
|
|
|
|
/**
|
|
* \brief Retrieve threshold state
|
|
*/
|
|
void _adc_sync_get_threshold_state(const struct _adc_sync_device *const device, adc_threshold_status_t *const state)
|
|
{
|
|
*state = hri_adc_get_interrupt_WINMON_bit(device->hw);
|
|
}
|
|
|
|
/**
|
|
* \brief Retrieve threshold state
|
|
*/
|
|
void _adc_async_get_threshold_state(const struct _adc_async_device *const device, adc_threshold_status_t *const state)
|
|
{
|
|
*state = hri_adc_get_interrupt_WINMON_bit(device->hw);
|
|
}
|
|
|
|
/**
|
|
* \brief Retrieve threshold state
|
|
*/
|
|
void _adc_dma_get_threshold_state(const struct _adc_dma_device *const device, adc_threshold_status_t *const state)
|
|
{
|
|
*state = hri_adc_get_interrupt_WINMON_bit(device->hw);
|
|
}
|
|
|
|
/**
|
|
* \brief Enable/disable ADC interrupt
|
|
*
|
|
* param[in] device The pointer to ADC device instance
|
|
* param[in] type The type of interrupt to disable/enable if applicable
|
|
* param[in] state Enable or disable
|
|
*/
|
|
void _adc_async_set_irq_state(struct _adc_async_device *const device, const uint8_t channel,
|
|
const enum _adc_async_callback_type type, const bool state)
|
|
{
|
|
(void)channel;
|
|
|
|
void *const hw = device->hw;
|
|
|
|
if (ADC_ASYNC_DEVICE_MONITOR_CB == type) {
|
|
hri_adc_write_INTEN_WINMON_bit(hw, state);
|
|
} else if (ADC_ASYNC_DEVICE_ERROR_CB == type) {
|
|
hri_adc_write_INTEN_OVERRUN_bit(hw, state);
|
|
} else if (ADC_ASYNC_DEVICE_CONVERT_CB == type) {
|
|
hri_adc_write_INTEN_RESRDY_bit(hw, state);
|
|
}
|
|
}
|
|
|
|
/**
|
|
* \brief SetADC resolution
|
|
*
|
|
* \param[in] hw The pointer to hardware instance
|
|
* \param[in] resolution The resolution to set
|
|
*/
|
|
static void _adc_set_resolution(void *const hw, const adc_resolution_t resolution)
|
|
{
|
|
bool enabled = hri_adc_get_CTRLA_ENABLE_bit(hw);
|
|
|
|
hri_adc_clear_CTRLA_ENABLE_bit(hw);
|
|
hri_adc_write_CTRLB_RESSEL_bf(hw, resolution);
|
|
|
|
if (enabled) {
|
|
hri_adc_set_CTRLA_ENABLE_bit(hw);
|
|
}
|
|
}
|
|
|
|
/**
|
|
* \brief SetADC resolution
|
|
*
|
|
* \param[in] hw The pointer to hardware instance
|
|
* \param[in] mode The mode to set
|
|
*/
|
|
static void _adc_set_conversion_mode(void *const hw, const enum adc_conversion_mode mode)
|
|
{
|
|
bool enabled = hri_adc_get_CTRLA_ENABLE_bit(hw);
|
|
|
|
hri_adc_clear_CTRLA_ENABLE_bit(hw);
|
|
hri_adc_clear_CTRLB_FREERUN_bit(hw);
|
|
if (ADC_CONVERSION_MODE_FREERUN == mode) {
|
|
hri_adc_set_CTRLB_FREERUN_bit(hw);
|
|
}
|
|
|
|
if (enabled) {
|
|
hri_adc_set_CTRLA_ENABLE_bit(hw);
|
|
}
|
|
}
|
|
|
|
/**
|
|
* \brief SetADC resolution
|
|
*
|
|
* \param[in] hw The pointer to hardware instance
|
|
* \param[in] mode The mode to set
|
|
*/
|
|
static void _adc_set_channel_differential_mode(void *const hw, const uint8_t channel,
|
|
const enum adc_differential_mode mode)
|
|
{
|
|
(void)channel;
|
|
bool enabled = hri_adc_get_CTRLA_ENABLE_bit(hw);
|
|
|
|
hri_adc_clear_CTRLA_ENABLE_bit(hw);
|
|
hri_adc_clear_CTRLB_DIFFMODE_bit(hw);
|
|
if (ADC_DIFFERENTIAL_MODE_DIFFERENTIAL == mode) {
|
|
hri_adc_set_CTRLB_DIFFMODE_bit(hw);
|
|
}
|
|
|
|
if (enabled) {
|
|
hri_adc_set_CTRLA_ENABLE_bit(hw);
|
|
}
|
|
}
|
|
|